US4935644A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Charge pump circuit having a boosted output signal
Assignee: Toshiba Corp
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Filing: 1988-08-04
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Granted: 1990-06-19
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Expires: 2008-08-04
Abstract
Abstract A semiconductor integrated circuit device is provided which comprises a first charge pumping circuit comprising a plurality of MOS transistors cascade-connected between an input voltage node and a booster output node, where, of all associated nodes, those odd-numbered nodes receive one of first and second clock signals through a corresponding capacitor and those even-numbered nodes receive the other clock signal through a corresponding capacitor, a second charge pumping circuit comprising a plurality of MOS transistors cascade-connected between the input voltage node and the booster output node and equal in number to those of the first charge pumping circuit where, of all associated nodes, those odd-numbered nodes receive one of first and second clock signals through a corresponding capacitor and those even-numbered nodes receive the other clock signal through a corresponding capacitor and the gates of the respective MOS transistors are connected to the gate of the corresponding MOS transistors, and a high resistive element connected to an output terminal of said first charge pumping circuit.
Inventors
- 👤 Jun-ichi Tsujimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:54
CPC Classifications
G; G11; G11C; G11C17/00; H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M3/073
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
101 words
A semiconductor integrated circuit device equipped with an internal booster circuit, comprising: a first boost-up circuit connected to a first input voltage node to receive a power source voltage; a second boost-up circuit including a plurality of second boost-up MOS transistors whose gates receive a voltage boosted up by the first boost-up circuit to compensate for a voltage drop resulting from a respective threshold voltage of the second boost-up MOS transistors; and a high resistive element connected between an output node of the first boost-up circuit and a potential terminal, to prevent an external current loss from the first boost-up circuit.
Claim 2
Dependent Claim
101 words
A semiconductor integrated circuit device equipped with an internal booster circuit, comprising: a first boost-up circuit connected to a first input voltage node to receive a power source voltage; a second boost-up circuit including a plurality of second boost-up MOS transistors whose gates receive a voltage boosted up by the first boost-up circuit to compensate for a voltage drop resulting from a respective threshold voltage of the second boost-up MOS transistors; and a high resistive element connected between an output node of the first boost-up circuit and a potential terminal, to prevent an external current loss from the first boost-up circuit.
Claim 3
Dependent Claim
123 words
The semiconductor integrated circuit device according to claim 1, in which said first boost-up circuit includes a first charge pumping circuit comprising a plurality of first boost-up MOS transistors connected in a cascaded fashion, and first boost-up connection nodes, each first boost-up connection node connected between a corresponding pair of the first boost-up MOS transistors, to serve as a plurality of boost-up stages, and said second boost-up circuit includes a second charge pumping circuit in which said plurality of second boost-up MOS transistors is cascade-connected and equal in number to those of said first charge pumping circuit and the respective gates of said second boost-up MOS transistors receive corresponding boost-up voltages from corresponding first boost-up connection nodes of said first charge pumping circuit.
Claim 4
Dependent Claim
105 words
The semiconductor integrated circuit device according to claim 2, in which said first boost-up circuit includes an internal boost-up circuit in which said plurality of first boost-up MOS transistors is cascade-connected between said first input node and said high resistive element with the gate of each first boost-up MOS transistor connected to the drain of the same transistor, in which, of first boost-up connection nodes connected between corresponding pairs of the first boost-up MOS transistors, those odd-numbered nodes receive one of first and second signals of a different phase through a corresponding capacitor and those even-numbered nodes receive the other signal through a corresponding capacitor.
Claim 5
Dependent Claim
139 words
The semiconductor integrated circuit device according to claim 2, in which said second boost-up circuit includes said second charge pumping circuit in which said plurality of second boost-up MOS transistors is cascade-connected between a second input voltage node and a second output node and equal in number to those of said first boost-up circuit, in which second boost-up connection nodes are provided, each second boost-up connection node connected between a corresponding pair of the second boost-up MOS transistors, those odd-numbered second boost-up connection nodes receive one of first and second signals of a different phase through a corresponding capacitor and those even-numbered second boost-up connection nodes receive the other signal through a corresponding capacitor, and the respective gate of each of said second boost-up MOS transistors is connected to a corresponding boost-up stage of said first charge pumping circuit.
Claim 6
Dependent Claim
139 words
The semiconductor integrated circuit device according to claim 3, in which said second boost-up circuit includes said second charge pumping circuit in which said plurality of second boost-up MOS transistors is cascade-connected between a second input voltage node and a second output node and equal in number to those of said first boost-up circuit, in which second boost-up connection nodes are provided, each second boost-up connection node connected between a corresponding pair of the second boost-up MOS transistors, those odd-numbered second boost-up connection nodes receive one of first and second signals of a different phase through a corresponding capacitor and those even-numbered second boost-up connection nodes receive the other signal through a corresponding capacitor, and the respective gate of each of said second boost-up MOS transistors is connected to a corresponding boost-up stage of said first charge pumping circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-18 | 1993-12-18 | 1994-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-18 | 1997-12-18 | 1998-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-18 | 2001-12-18 | 2002-06-19 | $7700.00 | Window Closed / Lapsed |