Low voltage CMOS logic circuit with threshold voltage control

Claim 2

A MOSFET circuit comprising: a first MOSFET having a first threshold voltage; and a second MOSFET having a second threshold voltage lower than or equal to said first threshold voltage, said second MOSFET having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to an external signal, wherein said second threshold voltage is lower than said first threshold.

Claim 3

A CMOS logic circuit including a series connection of a load transistor and a driver transistor, one of said driver transistor and said load transistor including a first MOSFET circuit, said first MOSFET circuit comprising: a first MOSFET having a first threshold voltage, and being connected to the other of said driver transistor and said load transistor; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET.

Claim 4

A CMOS logic circuit including a series connection of a load transistor and a driver transistor, one of said driver transistor and said load transistor including a first MOSFET circuit, said first MOSFET circuit comprising: a first MOSFET having a first threshold voltage, and being connected to the other of said driver transistor and said load transistor; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET.

Claim 5

The CMOS logic circuit as claimed in claim 2, wherein the other of said driver transistor and said load transistor is a MOSFET, and said CMOS logic circuit is a CMOS inverter.

Claim 6

The CMOS logic circuit as claimed in claim 2, wherein said load transistor comprises M (M is an integer greater than one) MOSFETs connected in series, and said driver transistor comprises M said first MOSFET circuits connected in parallel, and said CMOS logic circuit is a NOR circuit.

Claim 7

The CMOS logic circuit as claimed in claim 2, wherein said load transistor comprises M (M is an integer greater than one) MOSFETs connected in parallel, and said driver transistor comprises M said first MOSFET circuits connected in series, and said CMOS logic circuit is a NAND circuit.

Claim 8

The CMOS logic circuit as claimed in claim 2, wherein the other of said driver transistor and said load transistor includes a second MOSFET circuit, said second MOSFET comprising: a third MOSFET having a third threshold voltage, and being connected with said first MOSFET circuit in series; and a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

Claim 9

The CMOS logic circuit as claimed in claim 6, wherein said CMOS logic circuit is a CMOS inverter.

Claim 10

The CMOS logic circuit as claimed in claim 6, wherein said driver transistor comprises M (M is an integer greater than one) said first MOSFET circuits connected in parallel, and said load transistor comprises M said second MOSFET circuits connected in series, and said CMOS logic circuit is a NOR circuit.

Claim 11

The CMOS logic circuit as claimed in claim 6, wherein said driver transistor comprises M (M is an integer greater than one) said first MOSFET circuits connected in series, and said load transistor comprises M said second MOSFET circuits connected in parallel, and said CMOS logic circuit is a NAND circuit.

Claim 12

The CMOS logic circuit as claimed in claim 2, wherein each MOSFET of said CMOS logic circuit is a SOIFET which is formed on a SOI (Semiconductor On Insulator) substrate.

Claim 13

The CMOS logic circuit as claimed in claim 10, wherein carrier concentration of a body of said second MOSFET is controlled such that said body becomes a fully depleted state.

Claim 14

The CMOS logic circuit as claimed in claim 10, wherein carrier concentration of a body of said second MOSFET is controlled such that said body becomes a partially depleted state.

Claim 15

A buffer circuit including a first CMOS inverter and a second CMOS inverter alternately connected in cascade, wherein a load transistor of said first CMOS inverter comprises: a first MOSFET having a first threshold voltage, and being connected with a driver transistor of said first CMOS inverter in series; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, and wherein a driver transistor of said second CMOS inverter comprises: a third MOSFET having a third threshold voltage, and being connected with a load transistor of said second CMOS inverter in series; and a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

Claim 16

A buffer circuit including a first CMOS inverter and a second CMOS inverter alternately connected in cascade, wherein a load transistor of said first CMOS inverter comprises: a first MOSFET having a first threshold voltage, and being connected with a driver transistor of said first CMOS inverter in series; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, and wherein a driver transistor of said second CMOS inverter comprises: a third MOSFET having a third threshold voltage, and being connected with a load transistor of said second CMOS inverter in series; and a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

Claim 17

A CMOS logic circuit including a low threshold CMOS logic circuit and at least one switching circuit, said low threshold CMOS logic circuit including MOSFETs with a threshold voltage lower than a first threshold voltage, and said switching circuit being connected between a power supply terminal of said low threshold CMOS logic circuit and a power supply, wherein said switching circuit comprises: a first MOSFET having said first threshold voltage, and being connected between said power supply and said power supply terminal of said low threshold CMOS logic circuit; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET.

Claim 18

A CMOS logic circuit including a low threshold CMOS logic circuit and at least one switching circuit, said low threshold CMOS logic circuit including MOSFETs with a threshold voltage lower than a first threshold voltage, and said switching circuit being connected between a power supply terminal of said low threshold CMOS logic circuit and a power supply, wherein said switching circuit comprises: a first MOSFET having said first threshold voltage, and being connected between said power supply and said power supply terminal of said low threshold CMOS logic circuit; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET.

Claim 19

The CMOS logic circuit as claimed in claim 14, wherein said switching circuit is connected between a high potential terminal of said power supply and a high potential power supply terminal of said low threshold CMOS logic circuit.

Claim 20

The CMOS logic circuit as claimed in claim 14, wherein said switching circuit is connected between a low potential terminal of said power supply and a low potential power supply terminal of said low threshold CMOS logic circuit.

Claim 21

The CMOS logic circuit as claimed in claim 15, wherein said switching circuit is further connected between a low potential terminal of said power supply and a low potential power supply terminal of said low threshold CMOS logic circuit.

Claim 22

The CMOS logic circuit as claimed in claim 14, wherein said CMOS logic circuit is switched between a sleep mode and an active mode by a sleep signal externally fed, and further comprises a first buffer connected to a non-inverted sleep signal input terminal of said CMOS logic circuit, and a second buffer connected to an inverted sleep signal input terminal of said CMOS logic circuit, wherein said first buffer comprises a first CMOS inverter and a second CMOS inverter alternately connected in cascade, and a load transistor of said first CMOS inverter comprises: a first MOSFET having said first threshold voltage, and being connected with a driver transistor of said first CMOS inverter in series; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, wherein a driver transistor of said second CMOS inverter comprises: a third MOSFET having a third threshold voltage, and being connected with a load transistor of said second CMOS inverter in series; and a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET, and wherein said second buffer comprises said second CMOS inverter and said first CMOS inverter alternately connected in cascade.

Claim 23

The CMOS logic circuit as claimed in claim 14, wherein said CMOS logic circuit is switched between a sleep mode and an active mode by a sleep signal externally fed, and further comprises a buffer connected to a non inverted sleep signal input terminal of said CMOS logic circuit, wherein said buffer comprises a first CMOS inverter and a second CMOS inverter alternately connected in cascade, and a load transistor of said first CMOS inverter comprises: a first MOSFET having said first threshold voltage, and being connected with a driver transistor of said first CMOS inverter in series; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, and wherein a driver transistor of said second CMOS inverter comprises: a third MOSFET having a third threshold voltage, and being connected with a load transistor of said second CMOS inverter in series; and a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

Claim 24

The CMOS logic circuit as claimed in claim 14, wherein said CMOS logic circuit is switched between a sleep mode and an active mode by a sleep signal externally fed, and further comprises a buffer connected to an inverted sleep signal input terminal of said CMOS logic circuit, wherein said buffer comprises a first CMOS inverter and a second CMOS inverter alternately connected in cascade, wherein a driver transistor of said first CMOS inverter comprises: a first MOSFET having said first threshold voltage, and being connected with a load transistor of said first CMOS inverter in series; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, and wherein a load transistor of said second CMOS inverter comprises: a third MOSFET having a third threshold voltage, and being connected with a driver transistor of said second CMOS inverter in series; and a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

Claim 25

The CMOS logic circuit as claimed in claim 14, wherein each MOSFET of said CMOS logic circuit is a SOIFET which is formed on a SOI (Semiconductor On Insulator) substrate.

Claim 26

The CMOS logic circuit as claimed in claim 21, wherein carrier concentration of a body of each of said low threshold MOSFET is controlled such that said body becomes a fully depleted state.

Claim 27

The CMOS logic circuit as claimed in claim 21, wherein carrier concentration of a body of each said low threshold MOSFET is controlled such that said body becomes a partially depleted state.

Claim 28

A CMOS logic circuit comprising: an internal CMOS logic circuit including a set of M (M is an integer equal to or greater than one) driver transistors and a set of M load transistors, said internal CMOS logic circuit changing its operation mode in response to an external control signal; a first MOSFET connected to a first MOSFET circuit constituting one of said set of driver transistors and said set of load transistors, wherein said first MOSFET has a same channel type as said first MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET circuit, and a second main current electrode connected to said external control signal; and a second MOSFET connected to a second MOSFET circuit constituting the other of said set of driver transistors and said set of load transistors, wherein said second MOSFET has a same channel type as said second MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said second MOSFET circuit, and a second main current electrode connected to an inverted signal of said external control signal.

Claim 29

A CMOS logic circuit comprising: an internal CMOS logic circuit including a set of M (M is an integer equal to or greater than one) driver transistors and a set of M load transistors, said internal CMOS logic circuit changing its operation mode in response to an external control signal; a first MOSFET connected to a first MOSFET circuit constituting one of said set of driver transistors and said set of load transistors, wherein said first MOSFET has a same channel type as said first MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET circuit, and a second main current electrode connected to said external control signal; and a second MOSFET connected to a second MOSFET circuit constituting the other of said set of driver transistors and said set of load transistors, wherein said second MOSFET has a same channel type as said second MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said second MOSFET circuit, and a second main current electrode connected to an inverted signal of said external control signal.

Claim 30

The CMOS logic circuit as claimed in claim 24, wherein a threshold voltage of each of said first MOSFET and said second MOSFET is lower than a threshold voltage of MOSFETs included in said internal CMOS logic circuit.

Claim 31

The CMOS logic circuit as claimed in claim 25, wherein each MOSFET of said CMOS logic circuit is a SOIFET which is formed on a SOI (Semiconductor on Insulator) substrate, and wherein carrier concentration of a body of each of said low threshold MOSFET is controlled such that said body becomes a fully depleted state.

Claim 32

The CMOS logic circuit as claimed in claim 25, wherein each MOSFET of said CMOS logic circuit is a SOIFET which is formed on a SOI (Semiconductor on Insulator) substrate, and wherein carrier concentration of a body of each of said low threshold MOSFET is controlled such that said body becomes a partially depleted state.

Claim 33

A CMOS logic circuit comprising: an internal CMOS logic circuit including a set of M (M is an integer equal to or greater than one) driver transistors and a set of M load transistors, said internal CMOS logic circuit changing its operation mode in response to an external control signal; and a first MOSFET connected to a first MOSFET circuit constituting one of said set of driver transistors and said set of load transistors, wherein said first MOSFET has a same channel type as said first MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET circuit, and a second main current electrode connected to said external control signal; wherein said internal CMOS logic circuit comprises a memory cell, and said control signal is a word line signal.

Claim 34

A CMOS logic circuit comprising: an internal CMOS logic circuit including a set of M (M is an integer equal to or greater than one) driver transistors and a set of M load transistors, said internal CMOS logic circuit changing its operation mode in response to an external control signal; and a first MOSFET connected to a first MOSFET circuit constituting one of said set of driver transistors and said set of load transistors, wherein said first MOSFET has a same channel type as said first MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET circuit, and a second main current electrode connected to said external control signal; wherein said internal CMOS logic circuit comprises a memory cell, and said control signal is a word line signal.