US5821152A
Expired / Lapsed
US
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Methods of forming hemispherical grained silicon electrodes including multiple temperature steps
Assignee: Intellectual Discovery Co Ltd
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Filing: 1997-10-15
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Granted: 1998-10-13
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Expires: 2017-10-15
Abstract
Abstract A method of forming a hemispherical grained silicon electrode includes the steps of forming an amorphous silicon layer on an integrated circuit substrate, and heating the integrated circuit substrate and the amorphous silicon layer to a first deposition temperature. The amorphous silicon layer is exposed to a source gas including silicon while maintaining the first deposition temperature thereby forming silicon crystal nuclei on a surface of the amorphous silicon layer. The temperature of the integrated circuit substrate is lowered to a second deposition temperature wherein the second deposition temperature is less than the first deposition temperature. The silicon crystal nuclei are exposed to the source gas including silicon while maintaining the second deposition temperature thereby increasing a size of the silicon crystal nuclei. The silicon layer and the silicon crystal nuclei are then annealed thereby further increasing the size of the silicon crystal nuclei to provide hemispherical grains on the silicon layer.
Inventors
- 👤 Chan-hee Han
- 👤 Chang-jip Yang
- 👤 Young-kyou Park
- 👤 Jae-wook Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:58
CPC Classifications
H; H10; H10B; H10B12/00; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
167 words
A method of forming a hemispherical grained silicon electrode, said method comprising the steps of: forming an amorphous silicon layer on an integrated circuit substrate; heating said integrated circuit substrate and said amorphous silicon layer to a first deposition temperature; exposing said amorphous silicon layer to a source gas including silicon while maintaining said first deposition temperature thereby forming silicon crystal nuclei on a surface of said amorphous silicon layer; lowering a temperature of said integrated circuit substrate, said amorphous silicon layer, and said silicon crystal nuclei to a second deposition temperature wherein said second deposition temperature is less than said first deposition temperature; exposing said silicon crystal nuclei to said source gas including silicon while maintaining said second deposition temperature thereby increasing a size of said silicon crystal nuclei; and annealing said silicon layer and said silicon crystal nuclei after said step of exposing said silicon crystal nuclei thereby further increasing said size of said silicon crystal nuclei to provide hemispherical grains on said silicon layer.
Claim 2
Independent Claim
167 words
A method of forming a hemispherical grained silicon electrode, said method comprising the steps of: forming an amorphous silicon layer on an integrated circuit substrate; heating said integrated circuit substrate and said amorphous silicon layer to a first deposition temperature; exposing said amorphous silicon layer to a source gas including silicon while maintaining said first deposition temperature thereby forming silicon crystal nuclei on a surface of said amorphous silicon layer; lowering a temperature of said integrated circuit substrate, said amorphous silicon layer, and said silicon crystal nuclei to a second deposition temperature wherein said second deposition temperature is less than said first deposition temperature; exposing said silicon crystal nuclei to said source gas including silicon while maintaining said second deposition temperature thereby increasing a size of said silicon crystal nuclei; and annealing said silicon layer and said silicon crystal nuclei after said step of exposing said silicon crystal nuclei thereby further increasing said size of said silicon crystal nuclei to provide hemispherical grains on said silicon layer.
Claim 3
Dependent Claim
52 words
A method according to claim 1 wherein said heating step, said first exposing step, said lowering step, said second exposing step, and said annealing step are followed by the steps of: forming a dielectric layer on said silicon layer including said hemispherical grains; and forming an electrode layer on said dielectric layer.
Claim 4
Dependent Claim
37 words
A method according to claim 1 wherein said first deposition temperature is in the range of 570° C. to 600° C. and wherein said second deposition temperature is in the range of 550° C. to 590° C.
Claim 5
Dependent Claim
21 words
A method according to claim 1 wherein said second deposition temperature is in the range of 550° C. to 590° C.
Claim 6
Dependent Claim
28 words
A method according to claim 1 wherein said annealing step is performed at an annealing temperature, wherein said annealing temperature is no higher than said second deposition temperature.
Claim 7
Dependent Claim
29 words
A method according to claim 5 wherein said annealing step is performed while lowering said temperature of said silicon layer from said second deposition temperature to said annealing temperature.
Claim 8
Dependent Claim
32 words
A method according to claim 1 wherein said amorphous silicon layer is converted to polycrystalline silicon after said first exposing step, said lowering step, said second exposing step, and said annealing step.
Claim 9
Dependent Claim
27 words
A method according to claim 1 wherein said lowering step comprises exposing said amorphous silicon layer and said silicon crystal nuclei to said source gas including silicon.
Claim 10
Dependent Claim
17 words
A method according to claim 1 wherein said amorphous silicon layer comprises a doped amorphous silicon layer.
Claim 11
Dependent Claim
35 words
A method according to claim 1 wherein said heating step comprises stabilizing an environment surrounding said integrated circuit substrate at said first temperature for a predetermined period of time prior to said first exposing step.
Claim 12
Independent Claim
155 words
A method of forming a hemispherical grained silicon electrode, said method comprising the steps of: forming an amorphous silicon layer on an integrated circuit substrate; heating said integrated circuit substrate and said amorphous silicon layer to a first deposition temperature; exposing said amorphous silicon layer to a source gas including silicon while maintaining said first deposition temperature thereby forming silicon crystal nuclei on a surface of said amorphous silicon layer; exposing said silicon crystal nuclei to said source gas including silicon while lowering said temperature of said silicon layer to a second deposition temperature less than said first deposition temperature and maintaining said temperature of said silicon layer at said second deposition temperature thereby increasing a size of said silicon crystal nuclei; and annealing said silicon layer and said silicon crystal nuclei after said second exposing step thereby further increasing said size of said silicon crystal nuclei to provide hemispherical grains on said silicon layer.
Claim 13
Independent Claim
155 words
A method of forming a hemispherical grained silicon electrode, said method comprising the steps of: forming an amorphous silicon layer on an integrated circuit substrate; heating said integrated circuit substrate and said amorphous silicon layer to a first deposition temperature; exposing said amorphous silicon layer to a source gas including silicon while maintaining said first deposition temperature thereby forming silicon crystal nuclei on a surface of said amorphous silicon layer; exposing said silicon crystal nuclei to said source gas including silicon while lowering said temperature of said silicon layer to a second deposition temperature less than said first deposition temperature and maintaining said temperature of said silicon layer at said second deposition temperature thereby increasing a size of said silicon crystal nuclei; and annealing said silicon layer and said silicon crystal nuclei after said second exposing step thereby further increasing said size of said silicon crystal nuclei to provide hemispherical grains on said silicon layer.
Claim 14
Dependent Claim
47 words
A method according to claim 11 wherein said heating step, said first and second exposing steps, and said annealing step are followed by the steps of: forming a dielectric layer on said silicon layer including said hemispherical grains; and forming an electrode layer on said dielectric layer.
Claim 15
Dependent Claim
37 words
A method according to claim 11 wherein said first deposition temperature is in the range of 570° C. to 600° C. and wherein said second deposition temperature is in the range of 550° C. to 590° C.
Claim 16
Dependent Claim
21 words
A method according to claim 11 wherein said second deposition temperature is in the range of 550° C. to 590° C.
Claim 17
Dependent Claim
29 words
A method according to claim 11 wherein said annealing step is performed at an annealing temperature, and wherein said annealing temperature is no higher than said second deposition temperature.
Claim 18
Dependent Claim
29 words
A method according to claim 15 wherein said annealing step is performed while lowering said temperature of said silicon layer from said second deposition temperature to said annealing temperature.
Claim 19
Dependent Claim
27 words
A method according to claim 11 wherein said amorphous silicon layer is converted to polycrystalline silicon after said first and second exposing steps, and said annealing step.
Claim 20
Dependent Claim
17 words
A method according to claim 11 wherein said amorphous silicon layer comprises a doped amorphous silicon layer.
Claim 21
Dependent Claim
35 words
A method according to claim 11 wherein said heating step comprises stabilizing an environment surrounding said integrated circuit substrate at said first temperature for a predetermined period of time prior to said first exposing step.
Claim 22
Independent Claim
130 words
A method of forming a hemispherical grained silicon electrode on an integrated circuit substrate, said method comprising the steps of: exposing an amorphous silicon layer on the integrated circuit substrate to a source gas including silicon while maintaining said amorphous silicon layer at a first deposition temperature thereby forming silicon crystal nuclei on a surface of said amorphous silicon layer; lowering a temperature of said integrated circuit substrate, said amorphous silicon layer, and said silicon crystal nuclei to a second deposition temperature wherein said second deposition temperature is less than said first deposition temperature; and exposing said silicon crystal nuclei to said source gas including silicon while maintaining silicon layer at said second deposition temperature lower that said first deposition temperature thereby increasing a size of said silicon crystal nuclei.
Claim 23
Independent Claim
130 words
A method of forming a hemispherical grained silicon electrode on an integrated circuit substrate, said method comprising the steps of: exposing an amorphous silicon layer on the integrated circuit substrate to a source gas including silicon while maintaining said amorphous silicon layer at a first deposition temperature thereby forming silicon crystal nuclei on a surface of said amorphous silicon layer; lowering a temperature of said integrated circuit substrate, said amorphous silicon layer, and said silicon crystal nuclei to a second deposition temperature wherein said second deposition temperature is less than said first deposition temperature; and exposing said silicon crystal nuclei to said source gas including silicon while maintaining silicon layer at said second deposition temperature lower that said first deposition temperature thereby increasing a size of said silicon crystal nuclei.
Claim 24
Dependent Claim
47 words
A method according to claim 20 further comprising the step of: annealing said silicon layer and said silicon crystal nuclei after said step of exposing said silicon crystal nuclei thereby further increasing said size of said silicon crystal nuclei to provide hemispherical grains on said silicon layer.
Claim 25
Dependent Claim
52 words
A method according to claim 20 wherein said heating step, said first exposing step, said lowering step, said second exposing step, and said annealing step are followed by the steps of: forming a dielectric layer on said silicon layer including said hemispherical grains; and forming an electrode layer on said dielectric layer.
Claim 26
Dependent Claim
37 words
A method according to claim 20 wherein said first deposition temperature is in the range of 570° C. to 600° C. and wherein said second deposition temperature is in the range of 550° C. to 590° C.
Claim 27
Dependent Claim
21 words
A method according to claim 20 wherein said second deposition temperature is in the range of 550° C. to 590° C.
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