Patent US5817567A successfully refreshed from Google Patents.
US5817567A
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Shallow trench isolation method
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1997-04-07
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Granted: 1998-10-06
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Expires: 2017-04-07
Abstract
Abstract An improved method for implementing shallow trench isolation in integrated circuits is described. The method begins with the formation of trenches, through patterning and etching. These trenches are then filled with a conformal layer of silicon oxide. This is followed by overcoating with a layer of a hard material such as silicon nitride or boron nitride. Next, chemical-mechanical polishing is used to remove the hard layer everywhere except where it has filled the depressions that overlie the trenches. Then, a non-selective etch is used to remove the remaining hard layer material as well as some of the silicon oxide, so that a planar surface is maintained. Finally, chemical-mechanical polishing is used a second time to remove excess silicon oxide from above the trenches' surface.
Inventors
- 👤 Syun-Ming Jang
- 👤 Ying-Ho Chen
- 👤 Chen-Hua Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:39
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/05
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
198 words
A method for implementing shallow trench isolation in an integrated circuit, comprising the sequential steps of: providing a partially formed integrated circuit having a first upper surface; forming a layer of pad oxide on said first upper surface; depositng a layer of silicon nitride on said pad oxide layer; patterning and etching the silicon nitride and pad oxide layers so as to expose said first upper surface in selected areas; etching the selected areas to a depth whereby shallow trenches are formed; depositing a conformal layer of silicon oxide over the integrated circuit thereby forming a second upper surface that contours the first upper surface including forming depressions above said shallow trenches; depositing a layer of a hard material onto said second upper surface; by means of chemical-mechanical polishing, planarizing the second upper surface by removing material from said second upper surface until the hard material has been removed everywhere except in said depressions; etching the second surface, including the hard layer in the depressions, with a non-selective etchant until all hard material has been removed; and by means of chemical-mechanical polishing, removing material from the second upper surface down to the level of said first upper surface.
Claim 2
Independent Claim
198 words
A method for implementing shallow trench isolation in an integrated circuit, comprising the sequential steps of: providing a partially formed integrated circuit having a first upper surface; forming a layer of pad oxide on said first upper surface; depositng a layer of silicon nitride on said pad oxide layer; patterning and etching the silicon nitride and pad oxide layers so as to expose said first upper surface in selected areas; etching the selected areas to a depth whereby shallow trenches are formed; depositing a conformal layer of silicon oxide over the integrated circuit thereby forming a second upper surface that contours the first upper surface including forming depressions above said shallow trenches; depositing a layer of a hard material onto said second upper surface; by means of chemical-mechanical polishing, planarizing the second upper surface by removing material from said second upper surface until the hard material has been removed everywhere except in said depressions; etching the second surface, including the hard layer in the depressions, with a non-selective etchant until all hard material has been removed; and by means of chemical-mechanical polishing, removing material from the second upper surface down to the level of said first upper surface.
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein the thickness of said layer of pad oxide is between about 100 and 200 Angstroms.
Claim 4
Dependent Claim
21 words
The method of claim 1 wherein the thickness of said layer of silicon nitride is between about 1,000 and 2,000 Angstroms.
Claim 5
Dependent Claim
17 words
The method of claim 1 wherein said layer of silicon nitride is deposited by means of LPCVD.
Claim 6
Dependent Claim
19 words
The method of claim 1 wherein said selected areas comprise rectangles measuring between about 3,000 and about 5,000 Angstroms.
Claim 7
Dependent Claim
15 words
The method of claim 1 wherein said depth is between about 0.3 and 0.5 microns.
Claim 8
Dependent Claim
23 words
The method of claim 1 wherein said conformal layer of silicon oxide is deposited to a thickness between about 0.6 and 0.8 microns.
Claim 9
Dependent Claim
28 words
The method of claim 1 wherein depositing said conformal layer of silicon oxide further comprises APCVD O 3 TEOS or SACVD O 3 TEOS or HDPCVD silane oxide.
Claim 10
Dependent Claim
12 words
The method of claim 1 wherein the hard material is silicon nitride.
Claim 11
Dependent Claim
20 words
The method of claim 9 wherein the silicon nitride is deposited to a thickness between about 0.1 and 0.4 microns.
Claim 12
Dependent Claim
17 words
The method of claim 9 wherein the non-selective etchant is trifluoro methane with carbon tetrafluoride and argon.
Claim 13
Dependent Claim
18 words
The method of claim 11 wherein etching is performed at a temperature between about 50° and 100° C.
Claim 14
Dependent Claim
12 words
The method of claim 1 wherein the hard material is boron nitride.
Claim 15
Dependent Claim
20 words
The method of claim 13 wherein the boron nitride is deposited to a thickness between about 0.1 and 0.4 microns.
Claim 16
Dependent Claim
17 words
The method of claim 13 wherein the non-selective etchant is trifluoro methane with carbon tetrafluoride and argon.
Claim 17
Dependent Claim
18 words
The method of claim 15 wherein etching is performed at a temperature between about 50° and 100° C.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-05 | 2002-04-06 | 2002-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-05 | 2006-04-06 | 2006-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-05 | 2010-04-06 | 2010-10-06 | $7700.00 | Window Closed / Lapsed |