Method and system including memory patching utilizing a transmission control signal and circuit

Claim 2

A data processing system, comprising: a central processing unit for providing a first address value and communicating a plurality of control values; a system memory coupled to the central processing unit for selectively receiving the first address value and the plurality of control values, the system memory providing a first data value in response to the first address value and a portion of the plurality of control values; memory access control means for providing a transmission control signal and a second memory enable signal, the memory access control means being coupled to the central processing unit for receiving the first address value and the plurality of control values, the memory access control means generating the transmission control signal in response to one of the first address value and a first one of the plurality of control values, the memory access control means generating the second memory enable signal in response to the first address value; a second memory for storing a second data value and selectively providing the second data value in response to the second memory enable signal, the second memory being coupled to the memory access control means for receiving the second memory enable signal; and a transmission circuit coupled between the system memory and the central processing unit for selectively providing the first data value to the central processing unit when the transmission control signal is in a first logic state.

Claim 3

The data processing system of claim 1 wherein the second memory enable signal is asserted to prevent conflicts between said central processing unit and said memory access control means.

Claim 4

The data processing system of claim 1 wherein the second memory is a dual port memory.

Claim 5

The data processing system of claim 1 wherein the second memory is an electrically erasable memory.

Claim 6

The data processing system of claim 1, further comprising: a register for storing a bit which enables the second memory to be written with a plurality of data values provided by the central processing unit.

Claim 7

The data processing system of claim 1, further comprising: a register for storing a bit which enables the second memory to be read and disables the second memory from being written.

Claim 8

The data processing system of claim 1 wherein the data processing system is implemented on a single integrated circuit.

Claim 9

The data processing system of claim 1 wherein the second memory is a register.

Claim 10

The data processing system of claim 1, further comprising: a first register for communicating at least one of a mask value and a match value to said memory access control means.

Claim 11

The data processing system of claim 9, wherein the memory access control means comprises: a comparator coupled to the central processing unit for receiving the first address value and coupled to the first register for receiving at least one of the mask value and the match value, the comparator comparing the first address value and at least one of the mask value and the match value to provide a compare output value; and a memory encode and control circuit coupled to the comparator for receiving the compare output value and coupled to the central processing unit for receiving the first one of the plurality of control signals, the memory encode and control circuit providing the transmission control signal and the second memory enable signal in response thereto.

Claim 12

The data processing system of claim 10 wherein the comparator uses the mask value to mask a first portion of the first address value.

Claim 13

The data processing system of claim 11 wherein the first portion is a set of upper bits of the first address value.

Claim 14

The data processing system of claim 10, further comprising: a write patch control circuit for selectively providing a pending data value to the second memory in response to a system event signal in a first logic state.

Claim 15

The data processing system of claim 13 wherein an integrated circuit pin provides the system event signal.

Claim 16

The data processing system of 13 further comprising: an event comparator coupled to the central processing unit for receiving the first address value and a second one of the plurality of control values, the event comparator providing the system event signal in the first logic state in response to a preselected system event when the first address value corresponds to a pending address value.

Claim 17

The data processing system of 13 further comprising: an event comparator coupled to the central processing unit for receiving the first address value and a second one of the plurality of control values, the event comparator providing the system event signal in the first logic state in response to a preselected system event when the first address value corresponds to a pending address value.

Claim 18

The data processing system of 15 further comprising: a second register for communicating at least one of a pending mask value and the pending address value to the event comparator.

Claim 19

The data processing system of 15 further comprising: a second register for communicating at least one of a pending mask value and the pending address value to the event comparator.

Claim 20

The data processing system of 16 wherein the pending mask value masks a portion of the pending address value compared with the first address value by the event comparator.

Claim 21

The data processing system of 16 wherein the pending mask value masks a portion of the pending address value compared with the first address value by the event comparator.

Claim 24

The method of claim 18, further comprising the steps of: retrieving a first mask value from a mask register; and masking a first portion of the first address value before executing the step of comparing.

Claim 25

The method of claim 18, further comprising the steps of: detecting an occurrence of a system event; determining whether the system event is one of an external event and a processing event; and enabling a write patch control circuit to provide a pending data value to the second memory when the system event is the external event.

Claim 26

The method of claim 20, further comprising the steps of: comparing the one of the first address value and the first control value with the first match value when the system event is the processing event; executing no operation when the one of the first address value and the first control value does not correspond with the first match value; and enabling the write patch control circuit to provide the pending data value to the second memory when the system event is the processing event.

Claim 27

An emulation system, comprising: bus means for communicating a plurality of data values; a central processing unit for communicating a plurality of address values and a plurality of control values, the central processing unit coupled to the bus means for communicating the plurality of data values; a target memory coupled to the central processing unit for selectively receiving a first address value of the plurality of address values and the plurality of control values and coupled to the bus means for communicating the plurality of data values, the target memory providing a first data value to the bus means in response to the first address value and a portion of the plurality of control values; a memory access control circuit for providing a transmission control signal and a second memory enable signal, the memory access control circuit being coupled to the central processing unit for receiving the first address value and the plurality of control values, the memory access control circuit generating the transmission control signal in response to one of the first address value and a first one of the plurality of control values, the memory access control circuit generating the second memory enable signal in response to the first address value; a second memory for storing a second data value and selectively providing the second data value in response to the second memory enable signal, the second memory being coupled to the memory access control circuit for receiving the second memory enable signal; and a transmission circuit coupled to the bus means to selectively allow the bus means to provide the first data value to the central processing unit when the transmission control signal is in a first logic state.

Claim 28

An emulation system, comprising: bus means for communicating a plurality of data values; a central processing unit for communicating a plurality of address values and a plurality of control values, the central processing unit coupled to the bus means for communicating the plurality of data values; a target memory coupled to the central processing unit for selectively receiving a first address value of the plurality of address values and the plurality of control values and coupled to the bus means for communicating the plurality of data values, the target memory providing a first data value to the bus means in response to the first address value and a portion of the plurality of control values; a memory access control circuit for providing a transmission control signal and a second memory enable signal, the memory access control circuit being coupled to the central processing unit for receiving the first address value and the plurality of control values, the memory access control circuit generating the transmission control signal in response to one of the first address value and a first one of the plurality of control values, the memory access control circuit generating the second memory enable signal in response to the first address value; a second memory for storing a second data value and selectively providing the second data value in response to the second memory enable signal, the second memory being coupled to the memory access control circuit for receiving the second memory enable signal; and a transmission circuit coupled to the bus means to selectively allow the bus means to provide the first data value to the central processing unit when the transmission control signal is in a first logic state.

Claim 29

The emulation system of claim 22 wherein the memory access control circuit and the second memory are implemented on a single integrated circuit.

Claim 30

The emulation system of claim 22, further comprising: a first register for communicating at least one of a mask value and a match value to said memory access control circuit.

Claim 31

The emulation system of claim 24, wherein the memory access circuit comprises: a comparator coupled to the central processing unit for receiving the first address value and coupled to the first register for receiving at least one of the mask value and the match value, the comparator comparing the first address value and at least one of the mask value and the match value to provide a compare output value; and a memory encode and control circuit coupled to the comparator for receiving the compare output value and coupled to the central processing unit for receiving the first one of the plurality of control signals, the memory encode and control circuit providing the transmission control signal and the second memory enable signal in response thereto.

Claim 32

The emulation system of claim 25, wherein the memory access control circuit further comprises a write patch control circuit for selectively providing a pending data value to the second memory in response to a system event signal in a first logic state.

Claim 33

The data processing system of 26 further comprising: an event comparator coupled to the central processing unit for receiving the first address value and a second one of the plurality of control values, the event comparator providing the system event signal in the first logic state in response to a preselected system event when the first address value corresponds to a pending address value.

Claim 34

The data processing system of 26 further comprising: an event comparator coupled to the central processing unit for receiving the first address value and a second one of the plurality of control values, the event comparator providing the system event signal in the first logic state in response to a preselected system event when the first address value corresponds to a pending address value.