Single-chip microcomputer with memory patching capability

Claim 1

A single-chip microcomputer comprising: a data bus and an address bus; a first memory, connected to said data bus and said address bus, in which data necessary for data processing are set in a process of integrated circuit manufacture; a central processing unit, connected to said data bus and said address bus, for performing operations and control; a programmable counter, as part of said central processing unit, having an output connected to said address bus, for generating address data for accessing said first memory; a second memory, connected to said data bus and said address bus, capable of being electrically rewritten; a register with an input and an output, with said register input connected to said data bus, for setting a plurality of address data of said second memory in lieu of a plurality of address data of said first memory; and a coincidence circuit with a first input connected to said register output, a second input connected to said address bus, and an output connected to said central processing unit, for providing an interruption to said central processing unit upon detection of a coincidence between said register output and said programmable counter output; an I/O port, coupled to said address bus and to said data bus, for inputting data to be re-written to said second memory; and said central processing unit functioning to access an address of said second memory as a destination of said interruption upon provision thereof.