Computer having correctable read only memory

Claim 2

A computer comprising: a system bus; a central processing unit (CPU) connected to said system bus; main read only storage means connected to said system bus for storing main information; correction storage means connected to said system bus for storing substitute information to be substituted for at least one portion of said main information, said correction storage means being incorporated in said computer when a change of said portion is desired; and means connected to said system bus for detecting whether said correction storage means is incorporated into said computer and for generating a discrimination signal on said system bus having one of a first value definitely indicating that said correction storage means is incorporated into said computer, and a second value different from said first value definitely indicating that said correction storage means is not incorporated into said computer.

Claim 3

A computer according to claim 1, wherein said correction storage means comprises means for storing index data for designating said portion of said main information, said CPU being arranged to read said index data to determine which portion of said main information is to be replaced.

Claim 4

A computer according to claim 2, wherein said detecting means comprises a signal generator which produces said discrimination signal.

Claim 5

A computer according to claim 2, wherein said detecting means comprises a resistor one end of which is connected with a predetermined line of said system bus which is capable of transmitting information from said correction storage means to said CPU and the other end of which is connected with a voltage source having a first signal level corresponding to said second value, said correction storage means storing a bit corresponding to a second signal level, different from said first signal level and corresponding to said first value, at a predetermined storage location, said CPU operable to check a signal value on said predetermined line when accessing said predetermined storage location of said correction storage means and so determine whether said signal value is equal to said second signal level, thereby determining whether said correction storage means has been incorporated into said computer.

Claim 6

A computer according to claim 2, wherein said main information is a program, which is divided into a plurality of main blocks one of which includes said portion, said substitute information being a substitute block which is to be substituted for the main block which includes said portion, said index data being a designation of the main block which includes said portion, said CPU operable to enter said plurality of main blocks in sequence and to check, before entering a next main block whether said next main block is that designated by said index data, and, if it is, to enter said substitute block, and, if it is not, to enter said next main block.

Claim 7

A computer according to claim 2, wherein said main information is a program, which is divided into a plurality of main blocks, said substitute information is a substitute program divided into a plurality of corresponding substitute blocks which are to be substituted for some of said main blocks, said index data being designations of the main blocks each of which is to be replaced by a corresponding one of said substitute blocks, said CPU being operable, before entering each of said main blocks in said second case, to check whether that main block is designated to enter said plurality of main blocks in a sequence, and to check before entering a next main block, whether said next main block is one of those designated by said index data, and, if it is, to enter said corresponding substitute block, and, if it is not, to enter said next block.

Claim 8

A computer according to claim 6, wherein each of said designations is accompanied by address data which is also stored in said correction storage means and indicates a memory location where a first instruction of a corresponding substitute block is stored, said CPU being operable, when one of said main blocks is designated by one of said designations, to read the address data accompanying the designation currently being checked and to transfer control to a location indicated by the address data accompanying the designation currently being checked.

Claim 9

A computer comprising: a central processing unit (CPU); main read only storage means for storing main information; correction storage means for storing substitute information to be substituted for at least one portion of said main information; a system bus connected to said CPU, said main read only storage means, and said correction storage means, and having a first state in which said system bus interconnects said CPU with said main read only storage means but not with said correction storage means, and a second state in which said system bus interconnects said CPU with said correction storage means, but not with said main read only storage means; first comparing means connected to said system bus for comparing an address which said CPU is accessing with a first predetermined address and producing a first signal when a match is detected therebetween; second comparing means connected to said system bus for comparing the address which said CPU is accessing with a second predetermined address and producing a second signal when a match is detected therebetween; and selecting means connected to said system bus and connected with said first and second comparings means for changing said system bus from said first state to said second state in response to said first signal and from said second state to said first state in response to said second signal.

Claim 10

A computer comprising: a central processing unit (CPU); main read only storage means for storing main information; correction storage means for storing substitute information to be substituted for at least one portion of said main information; a system bus connected to said CPU, said main read only storage means, and said correction storage means, and having a first state in which said system bus interconnects said CPU with said main read only storage means but not with said correction storage means, and a second state in which said system bus interconnects said CPU with said correction storage means, but not with said main read only storage means; first comparing means connected to said system bus for comparing an address which said CPU is accessing with a first predetermined address and producing a first signal when a match is detected therebetween; second comparing means connected to said system bus for comparing the address which said CPU is accessing with a second predetermined address and producing a second signal when a match is detected therebetween; and selecting means connected to said system bus and connected with said first and second comparings means for changing said system bus from said first state to said second state in response to said first signal and from said second state to said first state in response to said second signal.

Claim 11

A computer according to claim 8, wherein said system bus comprises a data bus system and an address bus, and said data bus system further comprises: a first data bus connecting said CPU and said selecting means; a second data bus connecting said selecting means and said main read only storage means; and a third data bus connecting said selecting means and said correction storage means, said first data bus being connected with said second data bus and disconnected from said third data bus in said first state, said first data bus being connected with said third data bus and disconnected from said second data bus in said second state.

Claim 12

A computer comprising: a central processing unit (CPU); main read only storage means for storing main information; an output section for handling communication between said computer and outside devices; correction storage means for storing substitute information to be substituted for at least one portion of said main information; a system bus connected to said CPU, said main read only storage means, said output section, and said correction storage means, and having a first state in which said system bus interconnects said CPU with said main read only storage means but not with said correction storage means, and a second state in which said system bus interconnects said CPU with said correction storage means, but not with said main read only storage means; first comparing means connected to said system bus for comparing an address which said CPU is accessing with a predetermined address and producing a first signal if a match therebetween is detected; selecting means connected with said system bus and with said first comparing means for changing said system bus from said first state to said second state in response to said first signal; said output section being arranged to produce a second signal under control of an instruction stored in said correction storage means, said selecting means being connected with said output section and arranged to change said system bus from said second state to said first state in response to said second signal.

Claim 13

A computer comprising: a central processing unit (CPU); main read only storage means for storing main information; an output section for handling communication between said computer and outside devices; correction storage means for storing substitute information to be substituted for at least one portion of said main information; a system bus connected to said CPU, said main read only storage means, said output section, and said correction storage means, and having a first state in which said system bus interconnects said CPU with said main read only storage means but not with said correction storage means, and a second state in which said system bus interconnects said CPU with said correction storage means, but not with said main read only storage means; first comparing means connected to said system bus for comparing an address which said CPU is accessing with a predetermined address and producing a first signal if a match therebetween is detected; selecting means connected with said system bus and with said first comparing means for changing said system bus from said first state to said second state in response to said first signal; said output section being arranged to produce a second signal under control of an instruction stored in said correction storage means, said selecting means being connected with said output section and arranged to change said system bus from said second state to said first state in response to said second signal.

Claim 14

A computer according to claim 10, wherein said system bus comprises a data bus system and an address bus, and said data bus system further comprises: a first data bus connecting said CPU and said selecting means; a second data bus connecting said selecting means and said main read only storage means; and a third data bus connecting said selecting means and said correction storage means, said first data bus being connected with said second data bus and disconnected from said third data bus in said first state, said first data bus being connected with said third data bus and disconnected from said second data bus in said second state.

Claim 15

A computer comprising: a central processing unit (CPU); main read only storage means for storing main information; correction storage means for storing substitute information; a system bus connected to said CPU, said main read only storage means, and said correction storage means; comparing means connected to said system bus for comparing an address which said CPU is accessing with a first predetermined address of said main storage and producing a first signal when a match therebetween is detected; said CPU including interrupt handling means which, in response to said first signal from said comparing means, causes said CPU to fetch and use said substitute information instead of said main information and after that to return to said main information at a location having a second predetermined address, thereby to substitute said substitute information for a predetermined portion of said main information.

Claim 16

A computer comprising: a central processing unit (CPU); main read only storage means for storing main information; correction storage means for storing substitute information; a system bus connected to said CPU, said main read only storage means, and said correction storage means; comparing means connected to said system bus for comparing an address which said CPU is accessing with a first predetermined address of said main storage and producing a first signal when a match therebetween is detected; said CPU including interrupt handling means which, in response to said first signal from said comparing means, causes said CPU to fetch and use said substitute information instead of said main information and after that to return to said main information at a location having a second predetermined address, thereby to substitute said substitute information for a predetermined portion of said main information.

Claim 17

A computer according to claim 12, wherein said main information is a program, said first predetermined address is the address of a location where a first instruction of said predetermined portion of said main information is stored, and said second predetermined address is the address of a location where a next instruction immediately following said predetermined portion is stored.

Claim 18

A computer comprising: a system bus; a central processing unit (CPU) connected to said system bus; and main read only storage means connected to said system bus for storing main information; said computer being adapted to receive correction storage means for storing substitute information to replace at least one portion of said main information and for generating a signal on said system bus having one of a first value definitely indicating that said correction storage means has been connected into said computer and a second value different from said first value definitely indicating that said correction storage means has not been connected into said computer; and said CPU being adapted to respond to said signal when attempting to retrieve said at least one portion of said main information by retrieving said substitute information from said correction storage means when said signal has said first value, and by retrieving said at least one portion of said main information when said signal has said second value.

Claim 19

A computer comprising: a system bus; a central processing unit (CPU) connected to said system bus; and main read only storage means connected to said system bus for storing main information; said computer being adapted to receive correction storage means for storing substitute information to replace at least one portion of said main information and for generating a signal on said system bus having one of a first value definitely indicating that said correction storage means has been connected into said computer and a second value different from said first value definitely indicating that said correction storage means has not been connected into said computer; and said CPU being adapted to respond to said signal when attempting to retrieve said at least one portion of said main information by retrieving said substitute information from said correction storage means when said signal has said first value, and by retrieving said at least one portion of said main information when said signal has said second value.

Claim 20

Correction storage means comprising: means for storing substitute information to replace portions of main information stored in a main read only storage means in a computer; and means for generating a signal having one of a first value from which said computer can definitely determine that said correction storage means has been electronically incorporated therein and a second value different from said first value from wherein said computer can definitely determine that said correction storage means has not been incorporated therein; said computer adapted to receive said correction storage means and having a CPU adapted to retrieve said substitute information rather than said selected portions of said main information if said correction storage means has been electronically incorporated in said computer.

Claim 21

Correction storage means comprising: means for storing substitute information to replace portions of main information stored in a main read only storage means in a computer; and means for generating a signal having one of a first value from which said computer can definitely determine that said correction storage means has been electronically incorporated therein and a second value different from said first value from wherein said computer can definitely determine that said correction storage means has not been incorporated therein; said computer adapted to receive said correction storage means and having a CPU adapted to retrieve said substitute information rather than said selected portions of said main information if said correction storage means has been electronically incorporated in said computer.

Claim 22

A computer comprising: a system bus, a central processing unit (CPU) connected to said system bus; main read only storage means connected to said system bus for storing main information; correction storage means connected to said system bus for storing substitute information to be substituted for at least one portion of said main information, said correction storage means being incorporated in said computer when a change of said portion is desired; and means connected to said system bus for detecting whether said correction storage means is incorporated into said computer, said detecting means supplying a first signal to said CPU when said CPU performs a predetermined data transfer operation to move data from a predetermined address into said CPU while said correction storage means is not incorporated into said computer, and a second signal different from said first signal to said CPU when said CPU performs the predetermined data transfer operation while said correction storage means is incorporated into said computer, said CPU being adapted to determine whether said correction storage means is incorporated into said computer or not by performing the predetermined data transfer operation, and retrieve said substitute information instead of said portion of main information when said CPU determines that said correction storage means is incorporated into said computer.

Claim 23

A computer comprising: a system bus, a central processing unit (CPU) connected to said system bus; main read only storage means connected to said system bus for storing main information; correction storage means connected to said system bus for storing substitute information to be substituted for at least one portion of said main information, said correction storage means being incorporated in said computer when a change of said portion is desired; and means connected to said system bus for detecting whether said correction storage means is incorporated into said computer, said detecting means supplying a first signal to said CPU when said CPU performs a predetermined data transfer operation to move data from a predetermined address into said CPU while said correction storage means is not incorporated into said computer, and a second signal different from said first signal to said CPU when said CPU performs the predetermined data transfer operation while said correction storage means is incorporated into said computer, said CPU being adapted to determine whether said correction storage means is incorporated into said computer or not by performing the predetermined data transfer operation, and retrieve said substitute information instead of said portion of main information when said CPU determines that said correction storage means is incorporated into said computer.

Claim 24

A computer comprising: a system bus; a central processing unit (CPU) connected to said system bus; and main read only storage means connected to said system bus for storing main information, said computer being adapted to receive correction storage means for storing substitute information to replace at least one portion of said main information, said computer further comprising means connected to said system bus for detecting whether said correction storage means is incorporated into said computer, said detecting means supplying a first signal to said CPU when said CPU performs a predetermined data transfer operation to move data from a predetermined address into said CPU while said correction storage means is not incorporated into said computer, and a second signal different from said first signal to said CPU when said CPU performs the predetermined data transfer operation while said correction storage means is incorporated into said computer, and said CPU being adapted to determine whether said correction storage means is incorporated by performing the predetermined data transfer operation, and to retrieve said substitute information instead of said portion of said main information when said CPU determines that said correction storage means is incorporated.

Claim 25

A computer comprising: a system bus; a central processing unit (CPU) connected to said system bus; and main read only storage means connected to said system bus for storing main information, said computer being adapted to receive correction storage means for storing substitute information to replace at least one portion of said main information, said computer further comprising means connected to said system bus for detecting whether said correction storage means is incorporated into said computer, said detecting means supplying a first signal to said CPU when said CPU performs a predetermined data transfer operation to move data from a predetermined address into said CPU while said correction storage means is not incorporated into said computer, and a second signal different from said first signal to said CPU when said CPU performs the predetermined data transfer operation while said correction storage means is incorporated into said computer, and said CPU being adapted to determine whether said correction storage means is incorporated by performing the predetermined data transfer operation, and to retrieve said substitute information instead of said portion of said main information when said CPU determines that said correction storage means is incorporated.

Claim 26

A computer comprising: a system bus; a central processing unit (CPU) connected to said system bus; main read only storage means connected to said system bus for storing main information; correction storage means connected to said system bus for storing substitute information to be substituted for at least one portion of said main information, said correction storage means being incorporated in such computer when a change of said portion is desired; and detecting means comprising a resistor, one end of which is connected with an output line which is capable of transmitting a signal from said computer to an external device under command of said CPU, and the other end of which is connected with a predetermined line of said system bus which is capable of transmitting information from said correction storage means to said CPU; said CPU being arranged to perform a first check comprising reading a line value on said predetermined line of said system bus while said CPU is accessing a predetermined location of said correction storage means and placing a first predetermined value on said output line, and checking whether said line value is equal to said first predetermined value, and a second check comprising reading said line value on said predetermined line of said system bus while said CPU is accessing said predetermined location of said correction storage means and placing a second different predetermined value on said output line, and checking whether said line value is equal to said second predetermined value thereby detecting whether said correction storage means has been incorporated into said computer.

Claim 27

A computer comprising: a system bus; a central processing unit (CPU) connected to said system bus; main read only storage means connected to said system bus for storing main information; correction storage means connected to said system bus for storing substitute information to be substituted for at least one portion of said main information, said correction storage means being incorporated in such computer when a change of said portion is desired; and detecting means comprising a resistor, one end of which is connected with an output line which is capable of transmitting a signal from said computer to an external device under command of said CPU, and the other end of which is connected with a predetermined line of said system bus which is capable of transmitting information from said correction storage means to said CPU; said CPU being arranged to perform a first check comprising reading a line value on said predetermined line of said system bus while said CPU is accessing a predetermined location of said correction storage means and placing a first predetermined value on said output line, and checking whether said line value is equal to said first predetermined value, and a second check comprising reading said line value on said predetermined line of said system bus while said CPU is accessing said predetermined location of said correction storage means and placing a second different predetermined value on said output line, and checking whether said line value is equal to said second predetermined value thereby detecting whether said correction storage means has been incorporated into said computer.