US4769767A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory patching system
Assignee: NCR Voyix Corp
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Filing: 1984-01-03
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Granted: 1988-09-06
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Expires: 2004-01-03
Abstract
Abstract A data processing system comprising a central processing unit, a read-only memory, a changeable read-only memory and a read-write memory. A resident computer program is stored in the read-only memory, and instructions corresponding to program changes are stored in the changeable read-only memory. The program is assembled, revised and stored in the read-write memory from which the revised program can then be executed by the central processing unit. Other or further program revisions may be made by changing or reprogramming the changeable read-only memory.
Inventors
- 👤 Johan O. Hilbrink
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:26
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0638; G06F8/00; G06F8/60
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
297 words
In a memory patching system for a data processing system, a method comprising: storing in a plurality of addressable storage locations of a first memory means, a first page of a first set of instructions of a computer program; storing in a second memory means, a second set of instructions for revising said computer program, and a selected address of a storage location of the first page of the first instruction set stored in said first memory means identifying at least one instruction to be revised by said second set of instructions; transferring to a third memory means, said first page of said first set of instructions into a first plurality of memory locations thereof equal to the plurality of memory locations of said first page; comparing said selected address stored in said second memory means to the addresses of said storage locations in said first memory means of said first page of said first set of instructions transferred to said third memory means for identifying a revision location in said first plurality of memory locations of said third memory means; transferring said second set of instructions to a second plurality of memory locations of said third memory means; overwriting the instruction at said revision location in said first plurality of memory locations with a jump instruction for jumping to said second set of instructions in said second plurality of memory locations of said third memory means; and writing a second jump instruction at the end of said second set of instructions in said second plurality of memory locations in said third memory means for jumping back to the first set of instructions in said first plurality of memory locations in said third memory means such that a revision to the first set of instructions is effected.
Claim 2
Dependent Claim
297 words
In a memory patching system for a data processing system, a method comprising: storing in a plurality of addressable storage locations of a first memory means, a first page of a first set of instructions of a computer program; storing in a second memory means, a second set of instructions for revising said computer program, and a selected address of a storage location of the first page of the first instruction set stored in said first memory means identifying at least one instruction to be revised by said second set of instructions; transferring to a third memory means, said first page of said first set of instructions into a first plurality of memory locations thereof equal to the plurality of memory locations of said first page; comparing said selected address stored in said second memory means to the addresses of said storage locations in said first memory means of said first page of said first set of instructions transferred to said third memory means for identifying a revision location in said first plurality of memory locations of said third memory means; transferring said second set of instructions to a second plurality of memory locations of said third memory means; overwriting the instruction at said revision location in said first plurality of memory locations with a jump instruction for jumping to said second set of instructions in said second plurality of memory locations of said third memory means; and writing a second jump instruction at the end of said second set of instructions in said second plurality of memory locations in said third memory means for jumping back to the first set of instructions in said first plurality of memory locations in said third memory means such that a revision to the first set of instructions is effected.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-06 | 1992-03-07 | 1992-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-06 | 1996-03-07 | 1996-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-06 | 2000-03-07 | 2000-09-06 | $7700.00 | Window Closed / Lapsed |