Data transfer apparatus capable of handling DMA block transfer interruptions

Claim 1

A data transfer apparatus comprising: a plurality of direct memory access (DMA) channels having respective different priorities imparted thereto; at least one backup channel information memory for saving control information necessary for a restart of an interrupted DMA transfer through one of the plurality of the DMA channels, each of the at least one backup channel information memory being associated with at least one of the plurality of DMA channels; and control means responsive to a transfer command for commanding a DMA transfer through one of the plurality of DMA channels, wherein when a transfer command interrupts an execution of a DMA transfer through one of the plurality of DMA channels having a lower priority than the priority of one of the plurality of DMA channels used by the interrupting transfer command, the control means executes the following steps: 1) interrupting the DMA transfer through the DMA channel having the lower priority; 2) saving control information of the interrupted DMA transfer in one of the at least one backup channel information memory associated with the DMA channel having the lower priority; 3) executing the interrupting transfer command; 4) reading the saved control information of the interrupted DMA transfer from the backup channel information memory associated with the DMA channel having the lower priority; and 5) restarting the interrupted DMA transfer through the DMA channel having the lower priority after finishing the execution of the interrupting transfer command.