Boundary-scan testable system and method

Claim 5

A method as claimed in claim 2 additionally comprising, prior to said activating step, steps of: determining whether said data and control bus is already controlled by said Boundary-Scan master; and releasing control of said data and control bus when said data and control bus is already controlled by said Boundary-Scan master.

Claim 8

A method as claimed in claim 4 wherein said TAP controller is additionally for operating in an EXIT1-DR state, and said method additionally comprises, after said regulating step, steps of: identifying when said EXTEST instruction is loaded in said instruction register and said TAP controller has entered said EXIT1-DR state; determining, in response to said identifying step, whether said data and control bus is being controlled by said Boundary-Scan master; and releasing control of said data and control bus when said data and control bus is being controlled by said Boundary-Scan master.

Claim 9

A Boundary-Scan master for coupling to a data and control bus through which data defining Boundary-Scan tests are received, said Boundary-Scan master comprising: an arbitration interface; and control means, coupled to said arbitration interface, for determining when to request control of said data and control bus; wherein said Boundary-Scan master additionally comprises: means, coupled to said control means, for generating a test mode select (TMS) signal which controls Boundary-Scan testing of an integrated circuit (IC) having an instruction register and a test access port (TAP) controller for operating in a plurality of states, including a PAUSE-DR state; and said control means is configured to: cause said arbitration interface to generate a bus request output signal, and cause said generating means to control said TMS signal so that said TAP controller of said IC is held in said PAUSE-DR state until a bus granted input signal is received at said arbitration interface.

Claim 10

A Boundary-Scan master for coupling to a data and control bus through which data defining Boundary-Scan tests are received, said Boundary-Scan master comprising: an arbitration interface; and control means, coupled to said arbitration interface, for determining when to request control of said data and control bus; wherein said Boundary-Scan master additionally comprises: means, coupled to said control means, for generating a test mode select (TMS) signal which controls Boundary-Scan testing of an integrated circuit (IC) having an instruction register and a test access port (TAP) controller for operating in a plurality of states, including a PAUSE-DR state; and said control means is configured to: cause said arbitration interface to generate a bus request output signal, and cause said generating means to control said TMS signal so that said TAP controller of said IC is held in said PAUSE-DR state until a bus granted input signal is received at said arbitration interface.

Claim 11

A Boundary-Scan master as claimed in claim 6 wherein said control means is further configured to cause said generating means to control said TMS signal so that said TAP controller exits said PAUSE-DR state after said bus granted signal is received.

Claim 12

A Boundary-Scan master as claimed in claim 7 wherein said control means is further configured to: determine, prior to generation of said bus request output signal, whether said data and control bus is already being controlled by said Boundary-Scan master; and cause said arbitration interface to release control of said data and control bus when said data and control bus is already being controlled by said Boundary-Scan master.

Claim 13

A Boundary-Scan master for coupling to a data and control bus through which data defining Boundary-Scan tests are received, said Boundary-Scan master comprising: an arbitration interface; and control means, coupled to said arbitration interface, for determining when to request control of said data and control bus; wherein said Boundary-Scan master additionally comprises: means, coupled to said control means, for generating a test mode select (TMS) signal which controls Boundary-Scan testing of an integrated circuit (IC) having an instruction register and a test access port (TAP) controller for operating in a plurality of states, including an EXIT1-DR state, and for generating a test data output (TDO) signal which supplies data to said IC; and said control means is configured to cause said arbitration interface to request control of said data and control bus when an external test (EXTEST) instruction has been loaded in said instruction register of said IC through manipulation of said TMS and TDO signals and said TAP controller has passed through said EXIT1-DR state.

Claim 14

A Boundary-Scan master for coupling to a data and control bus through which data defining Boundary-Scan tests are received, said Boundary-Scan master comprising: an arbitration interface; and control means, coupled to said arbitration interface, for determining when to request control of said data and control bus; wherein said Boundary-Scan master additionally comprises: means, coupled to said control means, for generating a test mode select (TMS) signal which controls Boundary-Scan testing of an integrated circuit (IC) having an instruction register and a test access port (TAP) controller for operating in a plurality of states, including an EXIT1-DR state, and for generating a test data output (TDO) signal which supplies data to said IC; and said control means is configured to cause said arbitration interface to request control of said data and control bus when an external test (EXTEST) instruction has been loaded in said instruction register of said IC through manipulation of said TMS and TDO signals and said TAP controller has passed through said EXIT1-DR state.

Claim 15

A Boundary-Scan master for coupling to a data and control bus through which data defining Boundary-Scan tests are received, said Boundary-Scan master comprising: an arbitration interface; and control means, coupled to said arbitration interface, for determining when to request control of said data and control bus; wherein said Boundary-Scan master additionally comprises: means, coupled to said control means, for generating a test mode select (TMS) signal which controls Boundary-Scan testing of a Boundary-Scan integrated circuit (BSIC), wherein: said BSIC includes at least one output pin, core logic, an instruction register, a test access port (TAP) controller for operating in a plurality of states, including an UPDATE-DR state and a SHIFT-DR state, and a Boundary-Scan cell coupled between said core logic and said output pin; said BSIC is configured to isolate said output pin from said core logic during said UPDATE-DR state when said instruction register contains an external test (EXTEST) instruction; and said BSIC is further configured to couple said output pin to said core logic during said SHIFT-DR state when said instruction register contains said EXTEST instruction.

Claim 16

A Boundary-Scan master for coupling to a data and control bus through which data defining Boundary-Scan tests are received, said Boundary-Scan master comprising: an arbitration interface; and control means, coupled to said arbitration interface, for determining when to request control of said data and control bus; wherein said Boundary-Scan master additionally comprises: means, coupled to said control means, for generating a test mode select (TMS) signal which controls Boundary-Scan testing of a Boundary-Scan integrated circuit (BSIC), wherein: said BSIC includes at least one output pin, core logic, an instruction register, a test access port (TAP) controller for operating in a plurality of states, including an UPDATE-DR state and a SHIFT-DR state, and a Boundary-Scan cell coupled between said core logic and said output pin; said BSIC is configured to isolate said output pin from said core logic during said UPDATE-DR state when said instruction register contains an external test (EXTEST) instruction; and said BSIC is further configured to couple said output pin to said core logic during said SHIFT-DR state when said instruction register contains said EXTEST instruction.

Claim 17

A Boundary-Scan testable electronic system comprising: at least one Boundary-Scan integrated circuit (BSIC); a data and control bus; a Boundary-Scan master, coupled to said BSIC and said data and control bus, said Boundary-Scan master including an arbitration interface and a controller that determines when to request control of said data and control bus; and a bus arbitrator coupled to said arbitration interface, said bus arbitrator configured to grant control of said data and control bus; wherein said BSIC has an instruction register and a test access port (TAP) controller operable in a plurality of states, including a Pause-DR state; said master additionally comprises means, coupled to said control means, for generating a test mode select (TMS) signal which is fed to said BSIC and controls sequencing of said TAP controller through said states; and said controller is configured to: cause said arbitration interface to generate a bus request output signal which is fed to said bus arbitrator, and cause said generating means to control said TMS signal so that said TAP controller of said BSIC is held in said Pause-DR state until a bus granted input signal is received from said bus arbitrator at said arbitration interface.

Claim 18

A Boundary-Scan testable electronic system comprising: at least one Boundary-Scan integrated circuit (BSIC); a data and control bus; a Boundary-Scan master, coupled to said BSIC and said data and control bus, said Boundary-Scan master including an arbitration interface and a controller that determines when to request control of said data and control bus; and a bus arbitrator coupled to said arbitration interface, said bus arbitrator configured to grant control of said data and control bus; wherein said BSIC has an instruction register and a test access port (TAP) controller operable in a plurality of states, including a Pause-DR state; said master additionally comprises means, coupled to said control means, for generating a test mode select (TMS) signal which is fed to said BSIC and controls sequencing of said TAP controller through said states; and said controller is configured to: cause said arbitration interface to generate a bus request output signal which is fed to said bus arbitrator, and cause said generating means to control said TMS signal so that said TAP controller of said BSIC is held in said Pause-DR state until a bus granted input signal is received from said bus arbitrator at said arbitration interface.

Claim 19

A Boundary-Scan testable electronic system comprising: at least one Boundary-Scan integrated circuit (BSIC); a data and control bus; a Boundary-Scan master, coupled to said BSIC and said data and control bus, said Boundary-Scan master including an arbitration interface and a controller that determines when to request control of said data and control bus; and a bus arbitrator coupled to said arbitration interface, said bus arbitrator configured to grant control of said data and control bus; wherein said BSIC includes at least one output pin, core logic, an instruction register, a test access port (TAP) controller operable in a plurality of states, including an Update-DR state and a Shift-DR state, and a Boundary-Scan cell coupled between said core logic and said output pin; said BSIC is configured to isolate said output pin from said core logic during said Update-DR state when said instruction register contains an external test (EXTEST) instruction; and said BSIC is further configured to couple said output pin to said core logic during said Shift-DR state when said instruction register contains said EXTEST instruction.

Claim 20

A Boundary-Scan testable electronic system comprising: at least one Boundary-Scan integrated circuit (BSIC); a data and control bus; a Boundary-Scan master, coupled to said BSIC and said data and control bus, said Boundary-Scan master including an arbitration interface and a controller that determines when to request control of said data and control bus; and a bus arbitrator coupled to said arbitration interface, said bus arbitrator configured to grant control of said data and control bus; wherein said BSIC includes at least one output pin, core logic, an instruction register, a test access port (TAP) controller operable in a plurality of states, including an Update-DR state and a Shift-DR state, and a Boundary-Scan cell coupled between said core logic and said output pin; said BSIC is configured to isolate said output pin from said core logic during said Update-DR state when said instruction register contains an external test (EXTEST) instruction; and said BSIC is further configured to couple said output pin to said core logic during said Shift-DR state when said instruction register contains said EXTEST instruction.