Test apparatus and method for testing digital system

Claim 1

A digital electronic system testing apparatus for testing a plurality of electronic assemblies forming the system, each electronic assembly including a plurality of integrated circuits having leads for connecting the respective integrated circuit in the assembly, said leads respectively having boundary scan cells for testing the integrated circuits, the boundary scan cells of the leads of each integrated circuit being interconnected to form at least one shift register, each shift register having serial input means and serial output means and at least one clock line and one control line connected thereto from a control circuit, wherein the testing apparatus is capable of testing the assemblies even if some of the assemblies are missing or mispositioned, the testing apparatus comprising: means for interconnecting the at least one shift register of said integrated circuits forming each assembly to form at least one scan bus; means for interconnecting the thus formed at least one scan bus of at least one assembly together to form at least one assembly scan bus; a system scan bus; test computer means connected to said at least one assembly scan bus, via said system scan bus, for writing test data into and for reading test data out of said plurality of integrated circuits of an assembly, and for sending test address data to said assemblies; an additional control means in each assembly and operating as an interface between said system scan bus and said assembly scan bus, said additional control means being coupled between said at least one assembly scan bus and said system scan bus, said additional control means including: switching means for controllably disconnecting said system scan bus from said assembly scan bus; storage means for storing predetermined unique address data which uniquely identifies each assembly in the test apparatus; and comparing means for comparing said address data stored in said storage means with said test address data sent on said system scan bus; said switching means including means for connecting said assembly scan bus to said system scan bus when said comparing means determines, at a time when said system scan bus and said assembly scan bus are disconnected, that said address data in said storage means matches test address data.

Claim 5

A method for testing a digital electronic system comprising a plurality of electronic assemblies which form the system, each electronic assembly including a plurality of integrated circuits respectively having leads for interconnecting the integrated circuits in the assembly, said leads having boundary scan cells for testing the integrated circuits, and wherein the boundary scan cells of the leads of each integrated circuit are interconnected to form at least one shift register, each shift register having a serial input means and a serial output means, and each shift register further having at least one clock lead and one control lead thereof connected to a control circuit, said testing method permitting testing of assemblies even if some of the assemblies are missing or mispositioned during the testing of the system, the steps comprising: interconnecting the at least one shift register of said integrated circuits forming each assembly to form at least one scan bus; interconnecting the thus formed scan buses of at least one assembly to form at least one assembly scan bus; connecting test computer means to said at least one of said assemblies, via a system scan bus, for writing test data into and for reading data out of said integrated circuits in an assembly to be tested, and for sending test address data to said assemblies; providing, at each assembly, an additional control means between said at least one assembly scan bus of an assembly to be tested and said system scan bus, said additional control means including: first and second storage means; and switching means for controllably disconnecting said system scan bus from said assembly scan bus; disconnecting said system scan bus from said assembly scan bus with said controllable switching means before testing is to begin; storing predetermined unique address data which uniquely identifies the assembly to be tested, in said first storage means; storing test address data in said second storage means; said test address data being received from said test computer means via said system scan bus; comparing the data stored in said the first and second storage means; and connecting said assembly scan bus to said system scan bus when the comparing step indicates that data stored in said first and second storage means matches each other.

Claim 6

A method for testing a digital electronic system comprising a plurality of electronic assemblies which form the system, each electronic assembly including a plurality of integrated circuits respectively having leads for interconnecting the integrated circuits in the assembly, said leads having boundary scan cells for testing the integrated circuits, and wherein the boundary scan cells of the leads of each integrated circuit are interconnected to form at least one shift register, each shift register having a serial input means and a serial output means, and each shift register further having at least one clock lead and one control lead thereof connected to a control circuit, said testing method permitting testing of assemblies even if some of the assemblies are missing or mispositioned during the testing of the system, the steps comprising: interconnecting the at least one shift register of said integrated circuits forming each assembly to form at least one scan bus; interconnecting the thus formed scan buses of at least one assembly to form at least one assembly scan bus; connecting test computer means to said at least one of said assemblies, via a system scan bus, for writing test data into and for reading data out of said integrated circuits in an assembly to be tested, and for sending test address data to said assemblies; providing, at each assembly, an additional control means between said at least one assembly scan bus of an assembly to be tested and said system scan bus, said additional control means including: first and second storage means; and switching means for controllably disconnecting said system scan bus from said assembly scan bus; disconnecting said system scan bus from said assembly scan bus with said controllable switching means before testing is to begin; storing predetermined unique address data which uniquely identifies the assembly to be tested, in said first storage means; storing test address data in said second storage means; said test address data being received from said test computer means via said system scan bus; comparing the data stored in said the first and second storage means; and connecting said assembly scan bus to said system scan bus when the comparing step indicates that data stored in said first and second storage means matches each other.