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US5807779A
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Method of making tungsten local interconnect using a silicon nitride capped self-aligned contact process
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1997-07-30
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Granted: 1998-09-15
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Expires: 2017-07-30
Abstract
Abstract A process for fabricating MOSFET devices, using a local interconnect structure, and silicon nitride capped, self-aligned contact openings, has been developed. The process features the creation of self-aligned contact openings, exposing specific source and drain regions. After deposition of a composite insulator layer, a second opening is formed in the composite insulator layer, again exposing various elements including the previously opened, specific source and drain regions. The formation of a local interconnect structure, filling the second opening, contacts, as well as interconnects, the specific source and drain regions.
Inventors
- 👤 Jhon-Jhy Liaw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:02
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
326 words
A method of integrating elements of MOSFET devices, on a semiconductor substrate, via the use of a local interconnect structure, comprising the steps of: forming a field oxide region in said semiconductor substrate; forming a first polysilicon gate structure, and a second polysilicon gate structure, on a gate insulator layer, in a first region of said semiconductor substrate, and forming a third polysilicon gate structure, and a fourth polysilicon gate structure, on a gate insulator layer, in a second region of said semiconductor substrate, with said first region of said semiconductor substrate, and said second region of said semiconductor substrate, separated by said field oxide region; forming insulator sidewall spacers on the sides of the polysilicon gate structures; forming a first source and drain region, in a first region of said semiconductor substrate, between said first polysilicon gate structure, and said second polysilicon gate structure, and forming a second source and drain region, in said second region of said semiconductor substrate, between said third polysilicon gate structure, and said fourth polysilicon gate structure; depositing a first insulator layer, on all polysilicon gate structures, on all insulator sidewall spacers, and on all source and drain regions; forming a self-aligned contact, (SAC), opening, in said first insulator layer, exposing said first source and drain region, in said first region of said semiconductor substrate, and forming a SAC opening in said first insulator layer, exposing said second source and drain region, in said second region of said semiconductor substrate; depositing a second insulator layer, on said first insulator layer, and on said first source and drain region, and on said second source and drain region, exposed in SAC openings; forming a local interconnect opening in said second silicon insulator layer, exposing said first source and drain region, and said second source and drain region; and forming a local interconnect structure, in said local interconnect opening, contacting said first source and drain region, and said second source and drain region.
Claim 2
Independent Claim
326 words
A method of integrating elements of MOSFET devices, on a semiconductor substrate, via the use of a local interconnect structure, comprising the steps of: forming a field oxide region in said semiconductor substrate; forming a first polysilicon gate structure, and a second polysilicon gate structure, on a gate insulator layer, in a first region of said semiconductor substrate, and forming a third polysilicon gate structure, and a fourth polysilicon gate structure, on a gate insulator layer, in a second region of said semiconductor substrate, with said first region of said semiconductor substrate, and said second region of said semiconductor substrate, separated by said field oxide region; forming insulator sidewall spacers on the sides of the polysilicon gate structures; forming a first source and drain region, in a first region of said semiconductor substrate, between said first polysilicon gate structure, and said second polysilicon gate structure, and forming a second source and drain region, in said second region of said semiconductor substrate, between said third polysilicon gate structure, and said fourth polysilicon gate structure; depositing a first insulator layer, on all polysilicon gate structures, on all insulator sidewall spacers, and on all source and drain regions; forming a self-aligned contact, (SAC), opening, in said first insulator layer, exposing said first source and drain region, in said first region of said semiconductor substrate, and forming a SAC opening in said first insulator layer, exposing said second source and drain region, in said second region of said semiconductor substrate; depositing a second insulator layer, on said first insulator layer, and on said first source and drain region, and on said second source and drain region, exposed in SAC openings; forming a local interconnect opening in said second silicon insulator layer, exposing said first source and drain region, and said second source and drain region; and forming a local interconnect structure, in said local interconnect opening, contacting said first source and drain region, and said second source and drain region.
Claim 3
Dependent Claim
37 words
The method of claim 1, wherein said gate insulator layer is silicon dioxide, thermally grown, in an oxygen-steam ambient, at a temperature between about 850° to 1000° C., to a thickness between about 50 to 200 Angstroms.
Claim 4
Dependent Claim
72 words
The method of claim 1, wherein said polysilicon gate structures are a polycide layer, comprised of an underlying, N type, in situ doped, polysilicon layer, at a thickness between about 1000 to 2000 Angstroms, and an overlying tungsten silicide layer, at a thickness between about 500 to 1500 Angstroms, and capped with an overlying insulator layer of either silicon oxide, or silicon nitride, at a thickness between about 1000 to 3000 Angstroms.
Claim 5
Dependent Claim
52 words
The method of claim 1, wherein said first source and drain regions, and said second source and drain regions, are formed via ion implantation procedures, using either arsenic or phosphorous, at an energy between about 25 to 80 KeV, at a dose between about 1×10 15 to 6×10 15 atoms/cm 2 .
Claim 6
Dependent Claim
31 words
The method of claim 1, wherein said first insulator layer is a silicon nitride layer, deposited using either LPCVD or PECVD procedures, to a thickness between about 600 to 1000 Angstroms.
Claim 7
Dependent Claim
58 words
The method of claim 1, wherein said SAC opening, is formed via anisotropic etching of said first insulator layer, using CHF 3 and argon as an etchant, creating an opening between about 0.3 to 0.8 micrometer, in the spaces between said polysilicon gate structures, exposing said first source and drain region, and said second source and drain region.
Claim 8
Dependent Claim
60 words
The method of claim 1, wherein said second insulator layer is comprised of an underlying silicon nitride layer, at a thickness between about 200 to 400 Angstroms, and an overlying composite layer, comprised of a BPTEOS layer, at a thickness between about 3000 to 12000 Angstroms, overlying an undoped PETEOS layer, at a thickness between about 1000 to 2000 Angstroms.
Claim 9
Dependent Claim
46 words
The method of claim 7, wherein said local interconnect opening is formed in said second insulator layer via anisotropic RIE procedures, using CHF 3 as an etchant for the BPTEOS and PETEOS layers, while CHF 3 and argon is used as an etchant for silicon nitride.
Claim 10
Dependent Claim
55 words
The method of claim 1, wherein said local interconnect structure is deposited using LPCVD or r.f. sputtering procedures, to a thickness between about 4000 to 7000 Angstroms, and an underlying composite layer, comprised of titanium nitride layer on a titanium layer, deposited using r.f. sputtering procedures, at a thickness between about 500 to 1500 Angstroms.
Claim 11
Dependent Claim
22 words
The method of claim 1, wherein said local interconnect structure is formed via anisotropic RIE procedures, using SF 6 as an etchant.
Claim 12
Dependent Claim
17 words
The method of claim 1, wherein said local interconnect structure is formed via chemical mechanical polishing procedures.
Claim 13
Independent Claim
402 words
A method for connecting elements of MOSFET devices, on a semiconductor substrate, via use of a self-aligned, local interconnect structure, formed using silicon nitride capping SAC processing, comprising the steps of: forming a field oxide region in said semiconductor substrate; forming a first polysilicon gate structure, and a second polysilicon gate structure, on a gate insulator layer, in a first region of said semiconductor substrate, and forming a third polysilicon gate structure, and a fourth polysilicon gate structure, on a gate insulator layer, in a second region of said semiconductor substrate, with said first region of said semiconductor substrate, and said second region of said semiconductor substrate, separated by said field oxide region; forming insulator sidewall spacers on the sides of the polysilicon gate structures: forming a first heavily doped source and drain region in said first region of said semiconductor substrate, between said first polysilicon gate structure, and said second polysilicon gate structure, and forming a second heavily doped source and drain region in said second region of said semiconductor substrate, between said third polysilicon gate structure, and said fourth polysilicon gate structure; depositing a first silicon nitride layer on said polysilicon gate structures, on said insulator sidewall spacers, and on said heavily doped source and drain regions; forming a SAC opening, in said first silicon nitride layer, exposing said first heavily doped source and drain region, and forming a SAC opening, in said first silicon nitride layer, exposing said second heavily doped source and drain region; depositing a second silicon nitride layer, on said first silicon nitride layer, and on said first heavily doped source and drain region, and on said second heavily doped source and drain region, exposed in the SAC openings; depositing a composite interlevel dielectric layer on said second silicon nitride layer; forming a local interconnect opening in said interlevel dielectric layer, and in said second silicon nitride layer, exposing said first heavily doped source and drain region, and said second heavily doped source and drain region; depositing a composite layer of an underlying adhesive layer, and an overlying barrier layer, in said local interconnect opening; depositing a tungsten layer, the overlying barrier layer, of said composite layer; and an overlying; and patterning of said tungsten layer, and of said composite layer, to form said self-aligned local interconnect structure, contacting said first heavily doped source and drain region, and said second heavily doped source and drain region.
Claim 14
Independent Claim
402 words
A method for connecting elements of MOSFET devices, on a semiconductor substrate, via use of a self-aligned, local interconnect structure, formed using silicon nitride capping SAC processing, comprising the steps of: forming a field oxide region in said semiconductor substrate; forming a first polysilicon gate structure, and a second polysilicon gate structure, on a gate insulator layer, in a first region of said semiconductor substrate, and forming a third polysilicon gate structure, and a fourth polysilicon gate structure, on a gate insulator layer, in a second region of said semiconductor substrate, with said first region of said semiconductor substrate, and said second region of said semiconductor substrate, separated by said field oxide region; forming insulator sidewall spacers on the sides of the polysilicon gate structures: forming a first heavily doped source and drain region in said first region of said semiconductor substrate, between said first polysilicon gate structure, and said second polysilicon gate structure, and forming a second heavily doped source and drain region in said second region of said semiconductor substrate, between said third polysilicon gate structure, and said fourth polysilicon gate structure; depositing a first silicon nitride layer on said polysilicon gate structures, on said insulator sidewall spacers, and on said heavily doped source and drain regions; forming a SAC opening, in said first silicon nitride layer, exposing said first heavily doped source and drain region, and forming a SAC opening, in said first silicon nitride layer, exposing said second heavily doped source and drain region; depositing a second silicon nitride layer, on said first silicon nitride layer, and on said first heavily doped source and drain region, and on said second heavily doped source and drain region, exposed in the SAC openings; depositing a composite interlevel dielectric layer on said second silicon nitride layer; forming a local interconnect opening in said interlevel dielectric layer, and in said second silicon nitride layer, exposing said first heavily doped source and drain region, and said second heavily doped source and drain region; depositing a composite layer of an underlying adhesive layer, and an overlying barrier layer, in said local interconnect opening; depositing a tungsten layer, the overlying barrier layer, of said composite layer; and an overlying; and patterning of said tungsten layer, and of said composite layer, to form said self-aligned local interconnect structure, contacting said first heavily doped source and drain region, and said second heavily doped source and drain region.
Claim 15
Dependent Claim
37 words
The method of claim 12, wherein said gate insulator layer is silicon dioxide, thermally grown in an oxygen-steam ambient, at a temperature between about 850 to 1000° C., to a thickness between about 50 to 200 Angstroms.
Claim 16
Dependent Claim
76 words
The method of claim 12, wherein polysilicon gate structures are a polycide layer, comprised of an underlying, N type, in situ doped polysilicon layer, at a thickness between about 1000 to 2000 Angstroms, and an overlying tungsten silicide layer, at a thickness between about 500 to 1500 Angstroms, and with said polysilicon gate structures capped with an overlying silicon oxide layer, deposited using TEOS as a source, to a thickness between about 1000 to 3000 Angstroms.
Claim 17
Dependent Claim
44 words
The method of claim 12, wherein heavily doped source and drain regions are formed via ion implantation of either arsenic or phosphorous, at an energy between about 25 to 80 KeV, at a dose between about 1×10 15 to 6×10 15 atoms/cm 2 .
Claim 18
Dependent Claim
27 words
The method of claim 12, wherein said first silicon nitride layer is deposited using LPCVD or PECVD procedures, to a thickness between about 600 to 1000 Angstroms.
Claim 19
Dependent Claim
63 words
The method of claim 12, wherein said SAC opening, in said first silicon nitride layer, is formed via anisotropic RIE procedures, using CHF 3 and argon as an etchant, creating a space between about 0.3 to 0.8 micrometer, in width, between polysilicon gate structures, and exposing said first heavily doped source and drain region, and said second heavily doped source and drain region.
Claim 20
Dependent Claim
27 words
The method of claim 12, wherein said second silicon nitride layer, is deposited using LPCVD or PECVD procedures, to a thickness between about 200 to 400 Angstroms.
Claim 21
Dependent Claim
42 words
The method of claim 12, wherein said composite interlevel dielectric layer is comprised of an underlying, undoped PETEOS layer, at a thickness between about 1000 to 2000 Angstroms, and an overlying BPTEOS layer, at a thickness between about 3000 to 12000 Angstroms.
Claim 22
Dependent Claim
43 words
The method of claim 12, wherein said local interconnect opening is formed via anisotropic RIE of said composite interlevel dielectric layer, using CHF 3 as an etchant, and via anisotropic RIE of said second silicon nitride layer, using CHP 3 as an etchant.
Claim 23
Dependent Claim
39 words
The method of claim 12, wherein composite adhesive and barrier layer is deposited using r.f. sputtering, to a thickness between about 500 to 1500 Angstroms, comprised of an underlying titanium adhesive layer, and an overlying titanium nitride barrier layer.
Claim 24
Dependent Claim
23 words
The method of claim 12, wherein said tungsten layer is deposited using LPCVD procedures, to a thickness between about 4000 to 7000 Angstroms.
Claim 25
Dependent Claim
34 words
The method of claim 12, wherein said self-aligned local interconnect structure is formed via anisotropic RIE of said tungsten layer, and of said composite adhesive and barrier layer, using SF 6 as an etchant.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |