US5451545A
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US
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Process for forming stable local interconnect/active area silicide structure VLSI applications
Assignee: Advanced Micro Devices Inc
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Filing: 1994-09-21
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Granted: 1995-09-19
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Expires: 2014-09-21
Abstract
Abstract A local interconnect silicide structure (30) for connecting silicon regions (16) to silicon regions (20) separated by oxide regions (24) comprises a first portion of titanium silicide/titanium nitride/titanium silicide contacting the silicon regions and a second portion of titanium/titanium nitride/titanium silicide contacting the oxide regions. The silicide structure is also useful for connecting source/drain regions (14) and polysilicon interconnects (28). Two separate heating steps are employed, separated by an etch step to form the interconnects (34, 36). The first heating step forms (a) titanium silicides with single or polycrystalline silicon, using a first titanium layer (30a) at the bottom of the silicide structure and (b) titanium silicides with amorphous silicon (30d), using a second titanium layer (30c) on top of the titanium nitride layer (30b) on which the amorphous silicon is deposited and then patterned. The second heating step, which is at a higher temperature than the first, converts all the titanium silicides to titanium disilicide.
Inventors
- 👤 Seshadri Ramaswami
- 👤 Robin W. Cheung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:49
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10D; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/60; H10D64/62; H10W20/0698; H10W20/40; H10W20/41; H10W20/44; H10W20/4403; H10W20/4437; H10W20/4441; Y; Y10; Y10S; Y10S148/00; Y10S148/019
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
185 words
A process for forming local interconnect silicide structures for connecting silicon regions to silicon regions separated by oxide regions on a semiconductor wafer, comprising: (a) forming a stack layer comprising a first layer of titanium on said silicon and said oxide regions, a layer of titanium nitride on said first layer of titanium, a second layer of titanium on said layer of titanium nitride, and a layer of amorphous silicon on said second layer of titanium; (b) patterning and etching said layer of amorphous silicon to define said local interconnect silicide structures; (c) heating said stack layer at a first temperature to form titanium silicide wherever said first layer of titanium contacts said silicon regions and wherever there remains amorphous silicon on said second layer of titanium; (d) wet etching said stack layer to remove any unreacted titanium and titanium nitride remaining on said semiconductor wafer to form said local interconnect silicide structures; and (e) heating said stack layer at a second temperature above said first temperature to convert all titanium silicide in said stack layer that was formed in step (c) to titanium disilicide.
Claim 2
Dependent Claim
185 words
A process for forming local interconnect silicide structures for connecting silicon regions to silicon regions separated by oxide regions on a semiconductor wafer, comprising: (a) forming a stack layer comprising a first layer of titanium on said silicon and said oxide regions, a layer of titanium nitride on said first layer of titanium, a second layer of titanium on said layer of titanium nitride, and a layer of amorphous silicon on said second layer of titanium; (b) patterning and etching said layer of amorphous silicon to define said local interconnect silicide structures; (c) heating said stack layer at a first temperature to form titanium silicide wherever said first layer of titanium contacts said silicon regions and wherever there remains amorphous silicon on said second layer of titanium; (d) wet etching said stack layer to remove any unreacted titanium and titanium nitride remaining on said semiconductor wafer to form said local interconnect silicide structures; and (e) heating said stack layer at a second temperature above said first temperature to convert all titanium silicide in said stack layer that was formed in step (c) to titanium disilicide.
Claim 3
Dependent Claim
62 words
The process of claim 1 wherein said first layer of titanium ranges from about 250 to 600 Å, said layer of titanium nitride ranges from about 350 to 800 Å thick, said second layer of titanium ranges from about 300 to 1,000 Å, and said layer of silicon has a thickness of about 2 times that of said second layer of titanium.
Claim 4
Dependent Claim
35 words
The process of claim 1 wherein said stack layer is heated in step (c) to a temperature of about 350° to 650° C. for a period of time ranging from about 30 to 90 seconds.
Claim 5
Dependent Claim
34 words
The process of claim 1 wherein said etching in step (d) comprises subjecting said semiconductor wafer to an ammonium ion-containing solution to remove any unreacted titanium and titanium nitride remaining on said semiconductor wafer.
Claim 6
Dependent Claim
35 words
The process of claim 1 wherein said stack layer is heated in step (e) to a temperature of about 600° to 800° C. for a period of time ranging from about 15 to 60 seconds.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |