Patent US5807775A successfully refreshed from Google Patents.
US5807775A
Expired / Lapsed
US
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Method for forming a double walled cylindrical capacitor for a DRAM
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1996-06-24
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Granted: 1998-09-15
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Expires: 2016-06-24
Abstract
Abstract A method for manufacturing a double walled cylindrical stacked capacitor for a DRAM using only one photo mask is provided. An insulating layer having a contact opening is formed over a transistor. A first conductive layer is then formed over the insulating layer. The first conductive layer is patterned forming a central spine over the contact opening and portions of the first conductive layer are left covering the insulation layer. Dielectric spacers are formed on the sidewall of the central spine. The remaining portions of the first conductive layer over the first insulating layer are removed and upper portions of the central spine are removed forming a conductive base. Inner and outer conductive walls are formed on the sidewalls of the dielectric spacers thereby forming a double walled bottom electrode. The dielectric spacers are removed. A capacitor dielectric layer and a top electrode are formed over the bottom electrode forming the capacitor. The invention uses sidewall spacers and selective etching techniques to forms a low cost, simple to manufacture, high capacitance capacitor and DRAM cell.
Inventors
- 👤 Horng-Huei Tseng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:30
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
293 words
A method of forming a double walled cylindrical capacitor on a substrate having source regions, drain regions and gate electrode structures comprising: a) forming an insulating layer over a substrate surface; b) forming a contact opening exposing said source region; c) forming a first conductive layer over said insulating layer and filling said contact opening thereby forming an electrical contact with said source region; d) patterning said first conductive layer forming a central spine over said contact opening, and leaving portions of said first conductive layer covering said insulating layer, said central spine having sidewalls; e) forming a first dielectric layer over said portions of said first conductive layer and said central spine; f) anisotropically etching said first dielectric layer forming dielectric spacers on said sidewalls of said central spine, and on said portions of said first conductive layer; said dielectric spacers having sidewalls; g) anisotropically etching said portions of said first conductive layer over said insulating layer and etching back said central spine using said dielectric spacers as a mask forming a conductive base; said dielectric spacers on portions of said conductive base; said conductive base having sidewalls; h) forming a second conductive layer over said insulating layer, said conductive base, and said dielectric spacers; i) selectively etching said second conductive layer forming inner and outer conductive walls on the sidewalls of said dielectric spacers; said inner conductive wall on said conductive base and said outer conductive wall contacting said sidewalls of said conductive base thereby forming a bottom electrode having said conductive base electrically connecting said inner and outer conductive walls; j) removing said dielectric spacers; k) forming a capacitor dielectric layer and a top electrode over said bottom electrode and said insulating layer thereby forming a double walled cylindrical capacitor.
Claim 2
Independent Claim
293 words
A method of forming a double walled cylindrical capacitor on a substrate having source regions, drain regions and gate electrode structures comprising: a) forming an insulating layer over a substrate surface; b) forming a contact opening exposing said source region; c) forming a first conductive layer over said insulating layer and filling said contact opening thereby forming an electrical contact with said source region; d) patterning said first conductive layer forming a central spine over said contact opening, and leaving portions of said first conductive layer covering said insulating layer, said central spine having sidewalls; e) forming a first dielectric layer over said portions of said first conductive layer and said central spine; f) anisotropically etching said first dielectric layer forming dielectric spacers on said sidewalls of said central spine, and on said portions of said first conductive layer; said dielectric spacers having sidewalls; g) anisotropically etching said portions of said first conductive layer over said insulating layer and etching back said central spine using said dielectric spacers as a mask forming a conductive base; said dielectric spacers on portions of said conductive base; said conductive base having sidewalls; h) forming a second conductive layer over said insulating layer, said conductive base, and said dielectric spacers; i) selectively etching said second conductive layer forming inner and outer conductive walls on the sidewalls of said dielectric spacers; said inner conductive wall on said conductive base and said outer conductive wall contacting said sidewalls of said conductive base thereby forming a bottom electrode having said conductive base electrically connecting said inner and outer conductive walls; j) removing said dielectric spacers; k) forming a capacitor dielectric layer and a top electrode over said bottom electrode and said insulating layer thereby forming a double walled cylindrical capacitor.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein said insulating layer is formed of silicon oxide, and has a thickness in a range between about 1000 and 2000 Å.
Claim 4
Dependent Claim
28 words
The method of claim 1 wherein said first conductive layer is formed of polysilicon and has a thickness in a range of between about 1000 and 2000 Å.
Claim 5
Dependent Claim
21 words
The method of claim 1 wherein said central spine has a shape selected from the group consisting of cylindrical and rectangular.
Claim 6
Dependent Claim
29 words
The method of claim 1 wherein said first dielectric layer is composed of silicon nitride and has a thickness in a range of between about 500 and 2000 Å.
Claim 7
Dependent Claim
27 words
The method of claim 1 wherein said second conductive layer is formed polysilicon and has a thickness in a range of between about 500 and 2000 Å.
Claim 8
Dependent Claim
28 words
The method of claim 1 which further includes forming a top insulating layer and a metal layer over said double walled cylindrical capacitor thereby forming a DRAM cell.
Claim 9
Independent Claim
308 words
A method of forming a double walled cylindrical capacitor for a DRAM cell on a substrate having source regions, drain regions and gate electrode structures comprising: a) forming an insulating layer composed of silicon oxide over a substrate surface; b) forming a contact opening exposing said source region; c) forming a first conductive layer composed of doped polysilicon over said insulating layer and filling said contact opening thereby forming an electrical contact with said source region; d) patterning said first conductive layer forming a central spine over said contact opening, and leaving portions of said first conductive layer covering said insulating layer, said central spine having sidewalls; e) forming a first dielectric layer composed of silicon nitride over said portions of said first conductive layer and said central spine; f) anisotropically etching said first dielectric layer forming dielectric spacers on said sidewalls of said central spine, and on said portions of said first conductive layer; said dielectric spacers having sidewalls; g) anisotropically etching said portions of said first conductive layer over said insulating layer and etching back said central spine using said dielectric spacers as a mask forming a conductive base; said dielectric spacers on portions of said conductive base; said conductive base having sidewalls; h) forming a second conductive layer over said insulating layer, said conductive base, and said dielectric spacers; i) selectively etching said second conductive layer forming inner and outer conductive walls on the sidewalls of said dielectric spacers; said inner conductive wall on said conductive base; said outer conductive wall contacting said sidewalls of said conductive base thereby forming a bottom electrode having said conductive base electrically connecting said inner and outer conductive walls; j) removing said dielectric spacers; k) forming a capacitor dielectric layer and a top electrode over said bottom electrode and said insulating layer thereby forming a double walled cylindrical capacitor.
Claim 10
Independent Claim
308 words
A method of forming a double walled cylindrical capacitor for a DRAM cell on a substrate having source regions, drain regions and gate electrode structures comprising: a) forming an insulating layer composed of silicon oxide over a substrate surface; b) forming a contact opening exposing said source region; c) forming a first conductive layer composed of doped polysilicon over said insulating layer and filling said contact opening thereby forming an electrical contact with said source region; d) patterning said first conductive layer forming a central spine over said contact opening, and leaving portions of said first conductive layer covering said insulating layer, said central spine having sidewalls; e) forming a first dielectric layer composed of silicon nitride over said portions of said first conductive layer and said central spine; f) anisotropically etching said first dielectric layer forming dielectric spacers on said sidewalls of said central spine, and on said portions of said first conductive layer; said dielectric spacers having sidewalls; g) anisotropically etching said portions of said first conductive layer over said insulating layer and etching back said central spine using said dielectric spacers as a mask forming a conductive base; said dielectric spacers on portions of said conductive base; said conductive base having sidewalls; h) forming a second conductive layer over said insulating layer, said conductive base, and said dielectric spacers; i) selectively etching said second conductive layer forming inner and outer conductive walls on the sidewalls of said dielectric spacers; said inner conductive wall on said conductive base; said outer conductive wall contacting said sidewalls of said conductive base thereby forming a bottom electrode having said conductive base electrically connecting said inner and outer conductive walls; j) removing said dielectric spacers; k) forming a capacitor dielectric layer and a top electrode over said bottom electrode and said insulating layer thereby forming a double walled cylindrical capacitor.
Claim 11
Dependent Claim
22 words
The method of claim 8 wherein said insulating layer is has a thickness in a range between about 1000 and 2000 Å.
Claim 12
Dependent Claim
23 words
The method of claim 8 wherein said first conductive layer has a thickness in a range of between about 1000 and 2000 Å.
Claim 13
Dependent Claim
21 words
The method of claim 8 wherein said central spine has a shape selected from the group consisting of cylindrical and rectangular.
Claim 14
Dependent Claim
24 words
The method of claim 8 wherein said first dielectric layer is has a thickness in a range of between about 500 and 2000 Å.
Claim 15
Dependent Claim
23 words
The method of claim 8 wherein said second conductive layer has a thickness in a range of between about 500 and 2000 Å.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |