Patent US5805523A successfully refreshed from Google Patents.
US5805523A
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Burst counter circuit and method of operation thereof
Assignee: STMicroelectronics lnc USA
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Filing: 1997-04-04
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Granted: 1998-09-08
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Expires: 2017-04-04
Abstract
Abstract The decoded address signal is stored in the slave latch. The output of the slave latch is a column select signal. The slave latches are organized in a slave latch circuit which is connected as a counter. Each of the slave latches is treated as a register and four slave latches are combined to permit the sequential addresses selected to be in count up or count down as the slave latch circuit is clocked. In addition, a burst counter control circuit selectively controls the counter to produce a count in an interleaved mode or a count up mode. The least significant bit of the address is stored within the burst control circuit for indicating whether the count should be an up count or a down count when operating in the interleaved mode.
Inventors
- 👤 Mark A. Lysinger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:42
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
121 words
A circuit for addressing a plurality of addresses in a memory array from a single address input, comprising: an address input buffer for receiving a column address signal; a column address decoder circuit coupled to receive the column address signal and output a decoded column address signal; a counter circuit coupled to the column address decoder circuit to receive the decoded column address and output a column select signal, the counter circuit including a slave latch circuit for holding a current state of a column select signal; and a column select circuit coupled to the counter circuit for selecting the a pair of column lines within the memory array under control of the column select signal output by the counter circuit.
Claim 2
Dependent Claim
121 words
A circuit for addressing a plurality of addresses in a memory array from a single address input, comprising: an address input buffer for receiving a column address signal; a column address decoder circuit coupled to receive the column address signal and output a decoded column address signal; a counter circuit coupled to the column address decoder circuit to receive the decoded column address and output a column select signal, the counter circuit including a slave latch circuit for holding a current state of a column select signal; and a column select circuit coupled to the counter circuit for selecting the a pair of column lines within the memory array under control of the column select signal output by the counter circuit.
Claim 3
Dependent Claim
31 words
The circuit according to claim 1, further including: a column address predecoder coupled to the address input buffer and to the column address decoder for generating a predecoded column address signal.
Claim 4
Dependent Claim
33 words
The circuit according to claim 2, further including: a burst control circuit coupled to the counter circuit and to said predecoder circuit, said burst control circuit outputting controls signals to the counter circuit.
Claim 5
Dependent Claim
28 words
The circuit according to claim 3 wherein said counter circuit includes a shift register which shifts either up or down under the control of the burst control circuit.
Claim 6
Dependent Claim
37 words
The circuit according to claim 3, further including: an address latch circuit within the burst control circuit for holding column address information, the address information data state controlling whether the counter circuit counts up or counts down.
Claim 7
Dependent Claim
44 words
The circuit according to claim 3, further including: a count mode terminal connected to the burst counter for receiving a count mode signal; and mode logic connected to the count mode terminal for receiving a count mode and outputting a count pattern control signal.
Claim 8
Dependent Claim
26 words
The circuit according to claim 6 wherein said count pattern control signal controls the counter to count in either a linear pattern or an interleave pattern.
Claim 9
Dependent Claim
56 words
The circuit according to claim 3, further including: an encoder circuit within the burst control circuit and coupled to receive the input from the predecoder circuit and output the original address signal such that the address information stored in said address latch circuit within the burst control circuit includes a bit of the original address signal.
Claim 10
Dependent Claim
45 words
The circuit according to claim 1, further including: a master latch within the address input buffer for storing the column address data; and a slave latch within the counter circuit driven by the master latch that stores the same address data as the master latch.
Claim 11
Dependent Claim
112 words
A circuit comprising: a memory array having a plurality of memory cells therein; a plurality of bit lines coupled to the memory cell for accessing the memory cells; an address input buffer having a master latch therein for storing address information; a column address driver coupled to the master latch for driving the stored address information; a column address decoder coupled to the column address driver and outputting a decoded address signal; and a slave latch circuit coupled to the column address decoder for storing the decoded address information under control of the master latch, said slave latch circuit being connected to output column select signals directly to a column select circuit.
Claim 12
Dependent Claim
112 words
A circuit comprising: a memory array having a plurality of memory cells therein; a plurality of bit lines coupled to the memory cell for accessing the memory cells; an address input buffer having a master latch therein for storing address information; a column address driver coupled to the master latch for driving the stored address information; a column address decoder coupled to the column address driver and outputting a decoded address signal; and a slave latch circuit coupled to the column address decoder for storing the decoded address information under control of the master latch, said slave latch circuit being connected to output column select signals directly to a column select circuit.
Claim 13
Dependent Claim
52 words
The circuit according to claim 10, further including: a plurality of at least four slave latch circuits coupled to each other; a carry output signal lines from each slave latch and to adjacent slave latches; and a plurality of carry input signal lines to each slave latch circuit from adjacent slave latches.
Claim 14
Dependent Claim
34 words
The circuit according to claim 11, further including: a slave latch control circuit outputting control signals for causing the slave latches to transfer address information in either a count up or a count down.
Claim 15
Dependent Claim
58 words
The circuit according to claim 10, further including: an address clock signal line coupled to the input of the master latch in the address buffer and coupled to the input of the slave latch circuit such that both the master latch and slave latch receive address information that is input under the control of a common address clock.
Claim 16
Dependent Claim
49 words
The circuit according to claim 13, further including a burst counter clock coupled to the input of the slave latch and not coupled to the input of the master latch for inputting news address information into the slave latch while keeping the same address information in the master latch.
Claim 17
Dependent Claim
47 words
The circuit according to claim 13 wherein the slave latch circuit is coupled as a ring counter and address information from one slave latch is passed to an adjacent slave latch for providing new address information to the adjacent slave latch under control of the master clock.
Claim 18
Dependent Claim
37 words
The circuit according to claim 10, further,including: a clock circuit coupled to the slave latch for clocking the output of the slave latch at a selected rate while holding the address data constant in the master latch.
Claim 19
Independent Claim
149 words
A method of accessing address locations in a memory array having memory cells therein comprising: storing a column address in an address buffer having a master latch therein for storing the address information; decoding the column address and outputting the decoded address information; storing the decoded address information in a slave latch; outputting a column select signal from the slave latch; accessing memory cells in the memory array at locations specified by the decoded address information; changing the state of the address information in the slave latch to a new state without changing the state of the column address stored in the master latch of the address buffer; outputting a different column select signal from the slave latch based on the new state of the slave latch information; and accessing different memory cells in the array at different locations as specified by the new state of the address information.
Claim 20
Independent Claim
149 words
A method of accessing address locations in a memory array having memory cells therein comprising: storing a column address in an address buffer having a master latch therein for storing the address information; decoding the column address and outputting the decoded address information; storing the decoded address information in a slave latch; outputting a column select signal from the slave latch; accessing memory cells in the memory array at locations specified by the decoded address information; changing the state of the address information in the slave latch to a new state without changing the state of the column address stored in the master latch of the address buffer; outputting a different column select signal from the slave latch based on the new state of the slave latch information; and accessing different memory cells in the array at different locations as specified by the new state of the address information.
Claim 21
Dependent Claim
35 words
The method according to claim 17 wherein the step of changing the state of the address information in the slave latch includes shifting the address information from one slave latch to an adjacent slave latch.
Claim 22
Dependent Claim
22 words
The method according to claim 17, further including: controlling the changing of state in the slave latch from a burst controller circuit.
Claim 23
Dependent Claim
112 words
A circuit for addressing a plurality of addresses in a memory array from a single address input, comprising: an address input buffer for receiving a column address signal; a column address decoder circuit coupled to receive the column address signal and output a decoded column address signal; a counter circuit coupled to receive the decoded column address and output a column select signal, the counter circuit including a slave latch circuit for holding a current state of a column select signal; and a column select circuit coupled to the counter circuit for selecting a column line within the memory array under control of the column select signal output by the counter circuit.
Claim 24
Dependent Claim
112 words
A circuit for addressing a plurality of addresses in a memory array from a single address input, comprising: an address input buffer for receiving a column address signal; a column address decoder circuit coupled to receive the column address signal and output a decoded column address signal; a counter circuit coupled to receive the decoded column address and output a column select signal, the counter circuit including a slave latch circuit for holding a current state of a column select signal; and a column select circuit coupled to the counter circuit for selecting a column line within the memory array under control of the column select signal output by the counter circuit.
Claim 25
Dependent Claim
31 words
The circuit according to claim 20, further including: a column address predecoder coupled to the address input buffer and to the column address decoder for generating a predecoded column address signal.
Claim 26
Dependent Claim
33 words
The circuit according to claim 21, further including: a burst control circuit coupled to the counter circuit and to said predecoder circuit, said burst control circuit outputting controls signals to the counter circuit.
Claim 27
Dependent Claim
28 words
The circuit according to claim 22, wherein said counter circuit includes a shift register which shifts either up or down under the control of the burst control circuit.
Claim 28
Dependent Claim
110 words
A circuit comprising: a memory array having a plurality of memory cells therein; a bit line coupled to the memory cells for accessing the memory cells; an address input buffer having a master latch therein for storing address information; a column address driver coupled to the master latch for driving the stored address information; a column address decoder coupled to the column address driver and outputting a decoded address signal; and a slave latch circuit coupled to the column address decoder for storing the decoded address information under control of the master latch, said slave latch circuit being connected to output column select signals directly to a column select circuit.
Claim 29
Dependent Claim
110 words
A circuit comprising: a memory array having a plurality of memory cells therein; a bit line coupled to the memory cells for accessing the memory cells; an address input buffer having a master latch therein for storing address information; a column address driver coupled to the master latch for driving the stored address information; a column address decoder coupled to the column address driver and outputting a decoded address signal; and a slave latch circuit coupled to the column address decoder for storing the decoded address information under control of the master latch, said slave latch circuit being connected to output column select signals directly to a column select circuit.
Claim 30
Dependent Claim
31 words
The circuit according to claim 24, further including: a column address predecoder coupled to the address input buffer and to the column address decoder for generating a predecoded column address signal.
Claim 31
Dependent Claim
33 words
The circuit according to claim 25, further including: a burst control circuit coupled to the counter circuit and to said predecoder circuit, said burst control circuit outputting controls signals to the counter circuit.
Claim 32
Dependent Claim
28 words
The circuit according to claim 26, wherein said counter circuit includes a shift register which shifts either up or down under the control of the burst control circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-07 | 2002-03-09 | 2002-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-07 | 2006-03-09 | 2006-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-07 | 2010-03-09 | 2010-09-08 | $7700.00 | Window Closed / Lapsed |