US5804848A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field effect transistor having multiple gate electrodes surrounding the channel region
Assignee: Sony Corp
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Filing: 1997-10-31
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Granted: 1998-09-08
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Expires: 2017-10-31
Abstract
Abstract A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers induced in the channel region and enhance the current driving performance and mutual conductance as compared with the single gate structure or double gate structure.
Inventors
- 👤 Mikio Mukai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:33
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6735; H10D30/791; H10D30/798; H10D30/01; H10D30/021; H10D30/023; H10D30/031; H10D30/0321; H10D30/0323; H10D30/611; H10D30/62; H10D30/63; H10D30/6733; H10D30/6734; H10D30/6757; H10D30/797; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/013; H10D84/0135
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
102 words
A field effect transistor, comprising: a first impurity region formed in a semiconductor substrate, a channel region comprising a semiconductor layer formed on said first impurity region; a second impurity region formed on said channel regions, said first impurity region and said second impurity region forming a source region and a drain region, and gate electrodes formed by way of an insulation film or directly on the semiconductor substrate and to at least three surfaces of said channel region lateral of said substrate, wherein said gate electrodes are opposed respectively to the surfaces of said channel region and separated from each other.
Claim 2
Dependent Claim
102 words
A field effect transistor, comprising: a first impurity region formed in a semiconductor substrate, a channel region comprising a semiconductor layer formed on said first impurity region; a second impurity region formed on said channel regions, said first impurity region and said second impurity region forming a source region and a drain region, and gate electrodes formed by way of an insulation film or directly on the semiconductor substrate and to at least three surfaces of said channel region lateral of said substrate, wherein said gate electrodes are opposed respectively to the surfaces of said channel region and separated from each other.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-07 | 2002-03-09 | 2002-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-07 | 2006-03-09 | 2006-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-07 | 2010-03-09 | 2010-09-08 | $7700.00 | Window Closed / Lapsed |