Patent US5804477A successfully refreshed from Google Patents.
US5804477A
Expired / Lapsed
US
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Method of making a 6-transistor compact static ram cell
Assignee: Renesas Electronics America Inc
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Filing: 1997-02-24
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Granted: 1998-09-08
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Expires: 2017-02-24
Abstract
Abstract A 6-T SRAM cell having a MOS transistor with source/drain regions having an absence of heavily doped portions characteristic of prior art lightly doped drain (LDD) MOS devices is fabricated. Forming the MOS transistor with an absence of heavily doped portions of source/drain regions allows the width of the MOS gate layer, the width of the MOS source/drain regions and the width of the field oxide region between active regions of the SRAM cell to be reduced compared to the prior art. Accordingly, the present SRAM cell occupies less chip area than a prior art SRAM cell. Further, forming the MOS transistor without heavily doped portions of source/drain regions improves latch-up immunity and decreases write cycle time of the present SRAM cell.
Inventors
- 👤 Chuen-Der Lien
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:53
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0188; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
278 words
A method of fabricating a static random access memory (SRAM) cell comprising the steps of: providing a semiconductor substrate having first semiconductor regions with a first conductivity type and second semiconductor regions having a second conductivity type opposite said first conductivity type; forming first gates over portions of said first semiconductor regions and second gates over portions of said second semiconductor regions; implanting a second conductivity type impurity into portions of said first semiconductor regions to form source regions and drain regions of first and second metal oxide semiconductor (MOS) transistors in said first semiconductor regions, said source regions and said drain regions having said second conductivity type, wherein said first semiconductor regions have a first dopant concentration, wherein said source regions and said drain regions have a second dopant concentration and wherein said second dopant concentration is in the range of said first dopant concentration to 2.5 times said first dopant concentration; implanting a first conductivity type impurity into portions of said second semiconductor regions to form third semiconductor regions and fourth semiconductor regions, wherein third and fourth MOS transistors comprise said third semiconductor regions and said fourth semiconductor regions; and coupling said first MOS transistor between a first voltage source and a first node of said SRAM cell, said second MOS transistor between said first voltage source and a second node of said SRAM cell, said third MOS transistor between said first node and a second voltage source, said fourth MOS transistor between said second node and said second voltage source, gates of said first and third MOS transistors to said second node and gates of said second and fourth MOS transistors to said first node.
Claim 2
Independent Claim
278 words
A method of fabricating a static random access memory (SRAM) cell comprising the steps of: providing a semiconductor substrate having first semiconductor regions with a first conductivity type and second semiconductor regions having a second conductivity type opposite said first conductivity type; forming first gates over portions of said first semiconductor regions and second gates over portions of said second semiconductor regions; implanting a second conductivity type impurity into portions of said first semiconductor regions to form source regions and drain regions of first and second metal oxide semiconductor (MOS) transistors in said first semiconductor regions, said source regions and said drain regions having said second conductivity type, wherein said first semiconductor regions have a first dopant concentration, wherein said source regions and said drain regions have a second dopant concentration and wherein said second dopant concentration is in the range of said first dopant concentration to 2.5 times said first dopant concentration; implanting a first conductivity type impurity into portions of said second semiconductor regions to form third semiconductor regions and fourth semiconductor regions, wherein third and fourth MOS transistors comprise said third semiconductor regions and said fourth semiconductor regions; and coupling said first MOS transistor between a first voltage source and a first node of said SRAM cell, said second MOS transistor between said first voltage source and a second node of said SRAM cell, said third MOS transistor between said first node and a second voltage source, said fourth MOS transistor between said second node and said second voltage source, gates of said first and third MOS transistors to said second node and gates of said second and fourth MOS transistors to said first node.
Claim 3
Dependent Claim
94 words
A method as in claim 1 further comprising the steps of: forming a first masking layer over said first semiconductor regions prior to said step of implanting a first conductivity type impurity into portions of said second semiconductor regions to form third semiconductor regions and fourth semiconductor regions; removing said first masking layer; forming a second masking layer over said second semiconductor regions prior to said step of implanting a second conductivity type impurity into portions of said first semiconductor regions to form source regions and drain regions; and removing said second masking layer.
Claim 4
Dependent Claim
90 words
A method as in claim 1 wherein said first semiconductor regions are N-wells, said second semiconductor regions are P-wells, said second conductivity type is P type and said first conductivity type is N type further comprising the steps of: forming a masking layer over said P-wells and said N-wells; and performing an implantation with a P type impurity to form heavily doped source/drain regions having dopant concentrations equal to or greater than 1×10 18 atoms/cm 3 of devices formed in said semiconductor substrate which are external to said SRAM cell.
Claim 5
Dependent Claim
57 words
A method as in claim 1 further comprising the steps of: forming sidewall spacers adjacent edges of said first gates and said second gates; forming a first masking layer over said first semiconductor regions; and implanting a first conductivity type impurity into portions of said second semiconductor regions to form fifth semiconductor regions and sixth semiconductor regions.
Claim 6
Dependent Claim
53 words
A method as in claim 4 wherein said fifth semiconductor regions are laterally aligned with first ones of said sidewall spacers formed adjacent first edges of said second gates and wherein said sixth semiconductor regions are laterally aligned with second ones of said sidewall spacers formed adjacent second edges of said second gates.
Claim 7
Dependent Claim
35 words
A method as in claim 4 wherein said step of implanting a first conductivity type impurity into portions of said second semiconductor regions to form third semiconductor regions and fourth semiconductor regions comprising implanting phosphorus.
Claim 8
Dependent Claim
35 words
A method as in claim 5 wherein said step of implanting a first conductivity type impurity into portions of said second semiconductor regions to form fifth semiconductor regions and sixth semiconductor regions comprising implanting phosphorus.
Claim 9
Dependent Claim
88 words
A method as in claim 4 further comprising the steps of: removing said first masking layer; forming a second masking layer over said second semiconductor regions and said drain regions; and implanting a second conductivity type impurity into portions of said first semiconductor regions to form seventh semiconductor regions, said seventh semiconductor regions forming heavily doped portions of said source regions with a dopant concentration greater than said second dopant concentration, said seventh semiconductor regions being laterally aligned with sidewall spacers adjacent first edges of said first gates.
Claim 10
Dependent Claim
37 words
A method as in claim 1 wherein said third semiconductor regions are laterally aligned with first edges of said second gates and wherein said fourth semiconductor regions are laterally aligned with second edges of said second gates.
Claim 11
Dependent Claim
40 words
A method as in claim 1 wherein said step of implanting a second conductivity type impurity into portions of said first semiconductor regions to form source regions and drain regions is performed with a blanket second conductivity type impurity implant.
Claim 12
Dependent Claim
48 words
A method as in claim 10 further comprising, prior to said step of implanting a first conductivity type impurity into portions of said second semiconductor regions to form third semiconductor regions and fourth semiconductor regions, the step of forming a first masking layer over said first semiconductor regions.
Claim 13
Dependent Claim
41 words
A method as in claim 11 further comprising, prior to said step of implanting a second conductivity type impurity into portions of said first semiconductor regions to form source regions and drain regions, the step of removing said first masking layer.
Claim 14
Dependent Claim
42 words
A method as in claim 1 wherein said step of implanting a first conductivity type impurity into portions of said second semiconductor regions to form third semiconductor regions and fourth semiconductor regions is performed with a blanket first conductivity type impurity implant.
Claim 15
Dependent Claim
46 words
A method as in claim 13 further comprising, prior to said step of implanting a second conductivity type impurity into portions of said first semiconductor regions to form source regions and drain regions, the step of forming a first masking layer over said second semiconductor regions.
Claim 16
Dependent Claim
43 words
A method as in claim 14 further comprising, prior to said step of implanting a first conductivity type impurity into portions of said second semiconductor regions to form third semiconductor regions and fourth semiconductor regions, the step of removing said first masking layer.
Claim 17
Dependent Claim
39 words
A method as in claim 1 wherein said step of implanting a second conductivity type impurity into portions of said first semiconductor regions to form source regions and drain regions comprising implanting boron diflouride ions (BF 2 + ).
Claim 18
Dependent Claim
50 words
A method as in claim 16 wherein said source regions and said drain regions are continuous lightly doped semiconductor regions, said first and second MOS transistors having an absence of heavily doped portions of source regions or drain regions with dopant concentrations greater than 2.5 times said first dopant concentration.
Claim 19
Dependent Claim
35 words
A method as in claim 1 wherein said source regions are laterally aligned with first edges of said first gates and wherein said drain regions are laterally aligned with second edges of said first gates.
References Cited (Backward Citations)
US4740825A
Cited
US4823314A
Cited
US5016217A
Cited
US5072286A
Cited
US5134581A
Cited
US5225693A
Cited
US5298782A
Cited
US5310694A
Cited
US5334861A
Cited
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