Integrated circuit layout

Claim 1

A method for determining an integrated circuit layout on a surface of a semiconductor die, the integrated circuit including a plurality of components, at least two of the components including at least one pin, the type and structure of the components and the interconnections between pins of various components being predefined, the method comprising the steps of: determining a first component placement on the die surface, wherein: each component is represented as a block or one of a plurality of cells in a row of cells; a distance between adjacent cells within a row defines a cell spacing; and a region between defined locations of adjacent blocks and/or cell rows defines a channel having a channel height; and routing each interconnection, the step of routing further comprising the steps of: performing routing space estimation and adjustment to approximately define the routing demand, wherein, after the routing space estimation and adjustment step, the area of the die surface, each channel height and each cell spacing have a particular magnitude that together define a second component placement; and performing area-based detailed routing to exactly define the path of each interconnection, the magnitude of the die surface area after the detailed routing step remaining unchanged from the magnitude of the die surface area before the detailed routing step.

Claim 2

A method for determining an integrated circuit layout on a surface of a semiconductor die, the integrated circuit including a plurality of components, at least two of the components including at least one pin, the type and structure of the components and the interconnections between pins of various components being predefined, the method comprising the steps of: determining a first component placement on the die surface, wherein: each component is represented as a block or one of a plurality of cells in a row of cells; a distance between adjacent cells within a row defines a cell spacing; and a region between defined locations of adjacent blocks and/or cell rows defines a channel having a channel height; and routing each interconnection, the step of routing further comprising the steps of: performing routing space estimation and adjustment to approximately define the routing demand, wherein, after the routing space estimation and adjustment step, the area of the die surface, each channel height and each cell spacing have a particular magnitude that together define a second component placement; and performing area-based detailed routing to exactly define the path of each interconnection, the magnitude of the die surface area after the detailed routing step remaining unchanged from the magnitude of the die surface area before the detailed routing step.

Claim 29

A system for determining an integrated circuit layout on a surface of a semiconductor die, the integrated circuit including a plurality of components, at least two of the components including at least one pin, the type and structure of the components and the interconnections between pins of various components being predefined, the system comprising: means for determining a first component placement on the die surface, wherein: each component is represented as a block or one of a plurality of cells in a row of cells; a distance between adjacent cells within a row defines a cell spacing; and a region between defined locations of adjacent blocks and/or cell rows defines a channel having a channel height; and means for routing each interconnection, the means for routing further comprising: means for performing routing space estimation and adjustment to approximately define the routing demand, the performance of routing space estimation and adjustment resulting in the determination of a particular magnitude for the area of the die surface, each channel height and each cell spacing that together define a second component placement; and means for performing area-based detailed routing to exactly define the path of each interconnection, the magnitude of the die surface area after the detailed routing remaining unchanged from the magnitude of the die surface area before the detailed routing.

Claim 30

A system for determining an integrated circuit layout on a surface of a semiconductor die, the integrated circuit including a plurality of components, at least two of the components including at least one pin, the type and structure of the components and the interconnections between pins of various components being predefined, the system comprising: means for determining a first component placement on the die surface, wherein: each component is represented as a block or one of a plurality of cells in a row of cells; a distance between adjacent cells within a row defines a cell spacing; and a region between defined locations of adjacent blocks and/or cell rows defines a channel having a channel height; and means for routing each interconnection, the means for routing further comprising: means for performing routing space estimation and adjustment to approximately define the routing demand, the performance of routing space estimation and adjustment resulting in the determination of a particular magnitude for the area of the die surface, each channel height and each cell spacing that together define a second component placement; and means for performing area-based detailed routing to exactly define the path of each interconnection, the magnitude of the die surface area after the detailed routing remaining unchanged from the magnitude of the die surface area before the detailed routing.