Reduced skew differential receiver

Claim 3

The apparatus of claim 1, wherein the first signal path and the second signal path each include a differential amplifier.

Claim 4

The apparatus of claim 2, wherein the first signal path and the second signal path each include an active load.

Claim 5

The apparatus of claim 1, wherein the first type is a positive potential difference and the first transition is a low-to-high transition.

Claim 6

The apparatus of claim 4, wherein the second type is a negative potential difference and the second transition is a high-to-low transition.

Claim 7

A differential receiver comprising: a first input; a second input; an output; a first p-channel transistor, a second p-channel transistor, and a first current source including a first current mirror, the first p-channel transistor and second p-channel transistor each having a gate, a drain, and a source, the first current source having a first terminal connected to the source of the first p-channel transistor and the source of the second p-channel transistor and a second terminal connected to a first power supply voltage, the gate of the first p-channel transistor being connected to the first input and the gate of the second p-channel transistor being connected to the second input, wherein the first p-channel transistor, the second p-channel transistor, and the first current source form a first differential amplifier; a first n-channel transistor, a second n-channel transistor, and a second current source including a second current mirror, the first n-channel transistor and second n-channel transistor each having a gate, a drain, and a source, the second current source having a first terminal connected to the course of the first n-channel transistor and the source of the second n-channel transistor and a second terminal connected to a second power supply voltage, the gate of the first n-channel transistor being connected to the first input and the gate of the second n-channel transistor being connected to the second input, wherein the first n-channel transistor, the second n-channel transistor, and the second current source form a second differential amplifier; a third n-channel transistor and a fourth n-channel transistor, the third n-channel transistor and the fourth n-channel transistor each having a gate, a drain, and a source, the third n-channel transistor being a diode-connected transistor, the source of the third n-channel transistor and the source of the fourth n-channel transistor being connected to the second power supply voltage, the gate of the third n-channel transistor being connected to the gate of the fourth n-channel transistor, the drain of the third n-channel transistor being connected to the gate of the third n-channel transistor and to the drain of the second p-channel transistor, the drain of the fourth n-channel transistor being connected the output, the third n-channel transistor and the fourth n-channel transistor forming a first active load; and a third p-channel transistor and a fourth p-channel transistor, the third p-channel transistor and the fourth p-channel transistor each having a gate, a drain, and a source, the third p-channel transistor being a diode connected transistor, the source of the third p-channel transistor and the source of the fourth p-channel transistor being connected to the first power supply voltage, the gate of the third p-channel transistor being connected to the gate of the fourth p-channel transistor, the drain of the third p-channel transistor being connected to the gate of the third p-channel transistor and to the drain of the second n-channel transistor, the drain of the fourth p-channel transistor being connected to the output, the third p-channel transistor and the fourth p-channel transistor forming a second active load, wherein the first and second differential amplifiers and the first and second active loads are configured to limit skew between a first type of transition at the output and a second type of transition at the output to less than about one nanosecond.

Claim 8

A differential receiver comprising: a first input; a second input; an output; a first p-channel transistor, a second p-channel transistor, and a first current source including a first current mirror, the first p-channel transistor and second p-channel transistor each having a gate, a drain, and a source, the first current source having a first terminal connected to the source of the first p-channel transistor and the source of the second p-channel transistor and a second terminal connected to a first power supply voltage, the gate of the first p-channel transistor being connected to the first input and the gate of the second p-channel transistor being connected to the second input, wherein the first p-channel transistor, the second p-channel transistor, and the first current source form a first differential amplifier; a first n-channel transistor, a second n-channel transistor, and a second current source including a second current mirror, the first n-channel transistor and second n-channel transistor each having a gate, a drain, and a source, the second current source having a first terminal connected to the course of the first n-channel transistor and the source of the second n-channel transistor and a second terminal connected to a second power supply voltage, the gate of the first n-channel transistor being connected to the first input and the gate of the second n-channel transistor being connected to the second input, wherein the first n-channel transistor, the second n-channel transistor, and the second current source form a second differential amplifier; a third n-channel transistor and a fourth n-channel transistor, the third n-channel transistor and the fourth n-channel transistor each having a gate, a drain, and a source, the third n-channel transistor being a diode-connected transistor, the source of the third n-channel transistor and the source of the fourth n-channel transistor being connected to the second power supply voltage, the gate of the third n-channel transistor being connected to the gate of the fourth n-channel transistor, the drain of the third n-channel transistor being connected to the gate of the third n-channel transistor and to the drain of the second p-channel transistor, the drain of the fourth n-channel transistor being connected the output, the third n-channel transistor and the fourth n-channel transistor forming a first active load; and a third p-channel transistor and a fourth p-channel transistor, the third p-channel transistor and the fourth p-channel transistor each having a gate, a drain, and a source, the third p-channel transistor being a diode connected transistor, the source of the third p-channel transistor and the source of the fourth p-channel transistor being connected to the first power supply voltage, the gate of the third p-channel transistor being connected to the gate of the fourth p-channel transistor, the drain of the third p-channel transistor being connected to the gate of the third p-channel transistor and to the drain of the second n-channel transistor, the drain of the fourth p-channel transistor being connected to the output, the third p-channel transistor and the fourth p-channel transistor forming a second active load, wherein the first and second differential amplifiers and the first and second active loads are configured to limit skew between a first type of transition at the output and a second type of transition at the output to less than about one nanosecond.

Claim 9

The differential receiver of claim 6, wherein the first power supply voltage is an upper power supply voltage and the second power supply voltage is a lower power supply voltage.

Claim 10

The differential receiver of claim 7, wherein the upper power supply voltage is VDD.

Claim 11

The differential receiver of claim 7, wherein the lower power supply voltage is a ground voltage.

Claim 12

The differential receiver of claim 6, wherein the first p-channel transistor and the second p-channel transistor drive the fourth n-channel transistor directly and the first n-channel transistor and the second n-channel transistor drive the fourth p-channel transistor directly to generate a signal at the output.

Claim 13

The differential receiver of claim 6, wherein the first input is a negative input.

Claim 14

The differential receiver of claim 11, wherein the second input is a positive input.

Claim 15

A differential receiver comprising: a first input; a second input; an output; a first signal path from the first input to the output, the first signal path including: a first differential amplifier including a current mirror; and a first active load including a current mirror, wherein the first differential amplifier has a first terminal connected to a first power supply voltage and a second terminal connected to a second power supply voltage and a third terminal connected to the first active load and wherein the first differential amplifier has a connection to the first input and the second input and the first active load has a connection to the output; and a second signal path from the second input to the output, the second signal path including: a second differential amplifier including a current mirror; and a second active load including a current mirror, wherein the second differential amplifier has a first terminal connected to the second power supply voltage and a second terminal connected to the first power supply voltage and a third terminal connected to the second active load and wherein the second differential amplifier has a connection to the first input and the second input and the second active load has a connection to the output, wherein the first signal path and the second signal path both have an equal number of devices and output devices in the first active load and the second active load are driven by the first differential amplifier and the second differential amplifier and the first and second signal paths are configured to limit skew between a first type of transition at the output and a second type of transition at the output to less than about one nanosecond.

Claim 16

A differential receiver comprising: a first input; a second input; an output; a first signal path from the first input to the output, the first signal path including: a first differential amplifier including a current mirror; and a first active load including a current mirror, wherein the first differential amplifier has a first terminal connected to a first power supply voltage and a second terminal connected to a second power supply voltage and a third terminal connected to the first active load and wherein the first differential amplifier has a connection to the first input and the second input and the first active load has a connection to the output; and a second signal path from the second input to the output, the second signal path including: a second differential amplifier including a current mirror; and a second active load including a current mirror, wherein the second differential amplifier has a first terminal connected to the second power supply voltage and a second terminal connected to the first power supply voltage and a third terminal connected to the second active load and wherein the second differential amplifier has a connection to the first input and the second input and the second active load has a connection to the output, wherein the first signal path and the second signal path both have an equal number of devices and output devices in the first active load and the second active load are driven by the first differential amplifier and the second differential amplifier and the first and second signal paths are configured to limit skew between a first type of transition at the output and a second type of transition at the output to less than about one nanosecond.

Claim 17

The differential receiver of claim 13, wherein the first differential amplifier comprises a first transistor, a second transistor, and the first current mirror including a first current source, the first transistor and the second transistor each having a gate, a drain, and a source, the first current source having a first end connected to the source of the first transistor and the source of the second transistor and a second end connected to the first power supply voltage, the gate of the first transistor being connected to the first input and the gate of the second transistor being connected to the second input; and wherein the second differential amplifier comprises a third transistor, a fourth transistor, and the second current-mirror including a second current source, the third transistor and the fourth transistor each having a gate, a drain, and a source, the second current source having a first end connected to the source of the third transistor and the source of the fourth transistor and a second end connected to the second power supply voltage, the gate of the third transistor being connected to the first input and the gate of the fourth transistor being connected to the second input.

Claim 18

The differential receiver of claim 14, wherein the first transistor and the second transistor are p-channel metal-oxide-semiconductor transistors.

Claim 19

The differential receiver of claim 14, wherein the third transistor and the fourth transistor are n-channel metal-oxide-semiconductor transistors.

Claim 20

The receiver of claim 14, wherein the first active load comprises a fifth transistor and a sixth transistor, the fifth transistor and the sixth transistor each having a gate, a drain, and a source, the fifth transistor being a diode-connected transistor, the source of the fifth transistor and the source of the sixth transistor being connected to the second power supply voltage, the gate of the fifth transistor being connected to the gate of the sixth transistor, the drain of the fifth transistor being connected to the gate of the fifth transistor and to the drain of the second transistor, the drain of the sixth transistor being connected to the output; and wherein the second active load comprises a seventh transistor and an eighth transistor, the seventh transistor and the eighth transistor each having a gate, a drain, and a source, the seventh transistor being a diode-connected transistor, the source of the seventh transistor and the source of the eighth transistor being connected to the first power supply voltage, the gate of the seventh transistor being connected to the gate of the eighth transistor, the drain of the seventh transistor being connected to the gate of the seventh transistor and to the drain of the fourth transistor, the drain of the eighth transistor being connected the output.

Claim 21

The differential receiver of claim 17, wherein the fifth transistor and the sixth transistor are n-channel metal-oxide-semiconductor transistors.

Claim 22

The differential receiver of claim 17, wherein the seventh transistor and the eighth transistor are p-channel metal-oxide-semiconductor transistors.

Claim 23

The differential receiver of claim 13, wherein the first input is a negative input and the second input is a positive input.

Claim 24

The differential receiver of claim 13, wherein the first signal path causes a high-to-low voltage transition in a signal generated at the output.

Claim 25

The differential receiver of claim 13, wherein the second signal path causes a low-to-high voltage transition in a signal generated at the output.

Claim 26

A receiver comprising: a first input; a second input; an output, wherein high and low output voltages are generated by the output in response to input signals applied to the first input and the second input; a first differential amplifier and a second differential amplifier, each differential amplifier having a connection to the first input and a connection to the second input and the first differential amplifier having a number of devices identical to a number of devices within the second differential amplifier; and a first active load and a second active load, each active load having a connection to the output and the first active load having a number of devices identical to a number of devices within the second active load, wherein the first differential amplifier and the first active load are used to generate a high-to-low voltage transition at the output in response to a negative potential difference between the input signals applied to the first input and the second input and the second differential amplifier and the second active load are used to generate a low-to-high voltage transition in response to a positive potential difference between the input signals applied to the first input and the second input and wherein the devices within the first differential amplifier, the second differential amplifier, the first active load, and the second active load are configured to limit skew in the high-to-low voltage transition and the low-to-high voltage transition to less than about one nanosecond.

Claim 27

A receiver comprising: a first input; a second input; an output, wherein high and low output voltages are generated by the output in response to input signals applied to the first input and the second input; a first differential amplifier and a second differential amplifier, each differential amplifier having a connection to the first input and a connection to the second input and the first differential amplifier having a number of devices identical to a number of devices within the second differential amplifier; and a first active load and a second active load, each active load having a connection to the output and the first active load having a number of devices identical to a number of devices within the second active load, wherein the first differential amplifier and the first active load are used to generate a high-to-low voltage transition at the output in response to a negative potential difference between the input signals applied to the first input and the second input and the second differential amplifier and the second active load are used to generate a low-to-high voltage transition in response to a positive potential difference between the input signals applied to the first input and the second input and wherein the devices within the first differential amplifier, the second differential amplifier, the first active load, and the second active load are configured to limit skew in the high-to-low voltage transition and the low-to-high voltage transition to less than about one nanosecond.

Claim 28

The receiver of claim 23, wherein the devices within the first differential amplifier include a differential pair of p-channel transistors.

Claim 29

The receiver of claim 24, wherein the first active load includes a pair of n-channel transistors configured as a current mirror.

Claim 30

The receiver of claim 23, wherein the second differential amplifier includes a differential pair of n-channel transistors.

Claim 31

The receiver of claim 26, wherein the second active load includes a pair of p-channel transistors configured as a current mirror.

Claim 32

The receiver of claim 23, wherein the receiver has a common mode input range from about 0.7 V to about 1.8 V.

Claim 33

The receiver of claim 23, wherein a potential difference between the input signals applied to the first input and the second input range from about 70 mV to about 400 mV.