Method and apparatus for high-speed bi-CMOS differential amplifier with controlled output voltage swing

Claim 1

A high speed differential amplifier with controlled output voltage swing for amplifying low-level complementary logic signals, said differential amplifier comprised of: a) at least one sense amplifier containing a pair of load devices, said sense amplifier further having a first, second, third and fourth input, and a first and second output, said first input coupled to receive a first low-level logic signal, said second input coupled to receive a second low-level logic signal complementary to said first low-level logic signal, said third input coupled to receive a bias voltage from a load current control means for controlling the output voltage swing of said sense amplifier, and said fourth input coupled to receive an externally sourced enable signal, b) a load current control means for simulating said load devices in said amplifier, said load control means having a first input coupled to receive a reference swing voltage, a second input coupled to receive a simulated load voltage from a simulated load which simulates said load devices in the differential amplifier, and an output, said reference swing voltage comprising a desired voltage difference between a given high-level logic signal and its complementary high-level logic signal, said simulated load voltage comprising the voltage drop across a device geometrically similar to said load in the high speed differential amplifier, said load current control means comparing said simulated load voltage to said reference swing voltage and producing an output bias voltage corresponding to when the simulated voltage drop across said simulated load equals said reference swing voltage; said sense amplifier increasing said first and second low-level logic input signals to an amplified first and second high-level logic signals, said bias voltage controlling current flow in said load devices so that the output voltage swing of said first and second high-level logic signals is equal to said reference swing voltage, said first and second high-level logic signals comprising the controlled output swing of the differential amplifier.

Claim 32

A method for controlling the output voltage swing of a high speed differential amplifier for amplifying low-level complementary logic signals, said method comprised of the following steps: providing a load current control means having a first input coupled to receive a reference swing voltage, a second input coupled to receive a simulated load voltage from a simulated load, and an output, said load current control means comparing said simulated load voltage to said reference swing voltage and producing an output bias voltage corresponding to when the simulated voltage drop across said simulated load equals said reference swing voltage; and providing a sense amplifier having a first, second, third and fourth input, and a first and second output, said first input coupled to receive a first low-level logic signal, said second input coupled to receive a second low-level logic signal complementary to said first low-level logic signal, said third input coupled to receive said bias voltage for controlling the output voltage swing of said sense amplifier, and said fourth input coupled to receive an externally sourced enable signal, said sense amplifier increasing said first and second low-level logic input signals to an amplified first and second high-level logic signals, said bias voltage controlling said sense amplifier so that the output voltage swing of said first and second high-level logic signals is equal to said reference swing voltage, said first and second high-level logic signals comprising the controlled output swing of the differential amplifier.

Claim 33

A method for controlling the output voltage swing of a high speed differential amplifier for amplifying low-level complementary logic signals, said method comprised of the following steps: providing a load current control means having a first input coupled to receive a reference swing voltage, a second input coupled to receive a simulated load voltage from a simulated load, and an output, said load current control means comparing said simulated load voltage to said reference swing voltage and producing an output bias voltage corresponding to when the simulated voltage drop across said simulated load equals said reference swing voltage; and providing a sense amplifier having a first, second, third and fourth input, and a first and second output, said first input coupled to receive a first low-level logic signal, said second input coupled to receive a second low-level logic signal complementary to said first low-level logic signal, said third input coupled to receive said bias voltage for controlling the output voltage swing of said sense amplifier, and said fourth input coupled to receive an externally sourced enable signal, said sense amplifier increasing said first and second low-level logic input signals to an amplified first and second high-level logic signals, said bias voltage controlling said sense amplifier so that the output voltage swing of said first and second high-level logic signals is equal to said reference swing voltage, said first and second high-level logic signals comprising the controlled output swing of the differential amplifier.

Claim 34

A method for controlling the output voltage swing of a high speed differential amplifier for amplifying low-level complementary logic signals, said method comprised of the following steps: providing an emitter-coupled differential pair comprised of a first and second bipolar transistors; producing a reference swing voltage from a bipolar reference transistor, said reference swing voltage of magnitude V be equal to the base-emitter voltage, the emitter of said reference transistor connected to the base of said first transistor of the emitter-coupled differential pair; producing a simulated load voltage from a simulated load comprised of a p-channel transistor, said simulated load voltage corresponding to the current flowing in the simulated load, said simulated load connected to the base of said second bipolar transistor of said emitter-coupled differential pair; providing a voltage clamp; scaling the current and voltage corresponding to the voltage drop across said simulated load in a current mirror, said current mirror comprised of a first and second p-channel transistors, the drain of said second p-channel transistor comprising an input of said current mirror and connected to the collector of said second bipolar transistor of said emitter-coupled differential pair, and the drain of the first p-channel transistor comprising an output of said current mirror and connected to said voltage clamp, the difference between said reference swing voltage and said simulated load voltage appearing at the collector of said second transistor of said emitter-coupled pair and at the input of said current mirror, said scaled current and voltage corresponding to the voltage drop across said simulated load, said voltage clamp limiting said scaled voltage, the voltage-limited output of said voltage clamp comprising a desired bias voltage; providing an externally controlled enable switch comprised of an n-channel transistor, the gate of said enable switch driven by an enabling signal; providing a current source comprised of an n-channel transistor, the gate of said current source driven by said bias voltage; and amplifying in a sense amplifier a first and second low-level logic signals, said second low-level logic signal complementary to said first low-level logic signal, said sense amplifier comprised of a third and fourth bipolar transistors comprising an emitter coupled differential pair, said sense amplifier connected to receive a first and second low-level logic signals, said second low-level logic signal complementary to said first low-level logic signal, and the emitters of said third and fourth bipolar transistors switchably connected by said enable switch to said current source, and a first and second loads comprised of p-channel transistors connected, respectively, to said third and fourth bipolar transistors, said bias voltage controlling the current flow of said first and second low-level logic signals in said first and second loads respectively, the voltage corresponding to said controlled current flow in said first and second load comprising amplified first and second high-level controlled logic signals, said first and second high-level logic signals comprising said controlled output swing and appearing at said first and second outputs of said sense amplifier means is limited to said reference swing voltage.

Claim 35

A method for controlling the output voltage swing of a high speed differential amplifier for amplifying low-level complementary logic signals, said method comprised of the following steps: providing an emitter-coupled differential pair comprised of a first and second bipolar transistors; producing a reference swing voltage from a bipolar reference transistor, said reference swing voltage of magnitude V be equal to the base-emitter voltage, the emitter of said reference transistor connected to the base of said first transistor of the emitter-coupled differential pair; producing a simulated load voltage from a simulated load comprised of a p-channel transistor, said simulated load voltage corresponding to the current flowing in the simulated load, said simulated load connected to the base of said second bipolar transistor of said emitter-coupled differential pair; providing a voltage clamp; scaling the current and voltage corresponding to the voltage drop across said simulated load in a current mirror, said current mirror comprised of a first and second p-channel transistors, the drain of said second p-channel transistor comprising an input of said current mirror and connected to the collector of said second bipolar transistor of said emitter-coupled differential pair, and the drain of the first p-channel transistor comprising an output of said current mirror and connected to said voltage clamp, the difference between said reference swing voltage and said simulated load voltage appearing at the collector of said second transistor of said emitter-coupled pair and at the input of said current mirror, said scaled current and voltage corresponding to the voltage drop across said simulated load, said voltage clamp limiting said scaled voltage, the voltage-limited output of said voltage clamp comprising a desired bias voltage; providing an externally controlled enable switch comprised of an n-channel transistor, the gate of said enable switch driven by an enabling signal; providing a current source comprised of an n-channel transistor, the gate of said current source driven by said bias voltage; and amplifying in a sense amplifier a first and second low-level logic signals, said second low-level logic signal complementary to said first low-level logic signal, said sense amplifier comprised of a third and fourth bipolar transistors comprising an emitter coupled differential pair, said sense amplifier connected to receive a first and second low-level logic signals, said second low-level logic signal complementary to said first low-level logic signal, and the emitters of said third and fourth bipolar transistors switchably connected by said enable switch to said current source, and a first and second loads comprised of p-channel transistors connected, respectively, to said third and fourth bipolar transistors, said bias voltage controlling the current flow of said first and second low-level logic signals in said first and second loads respectively, the voltage corresponding to said controlled current flow in said first and second load comprising amplified first and second high-level controlled logic signals, said first and second high-level logic signals comprising said controlled output swing and appearing at said first and second outputs of said sense amplifier means is limited to said reference swing voltage.

Claim 36

A method for controlling the output voltage swing of a high speed differential amplifier for amplifying low-level complementary logic signals, said method comprised of the following steps: providing an emitter-coupled differential pair; producing a reference swing voltage; producing a simulated load voltage from a simulated load, said simulated load voltage corresponding to the current flowing in the simulated load; providing a voltage clamp; producing in a current mirror a scaled current and scaled voltage corresponding to the simulated voltage drop across said simulated load, said emitter-coupled pair producing a voltage difference between said reference swing voltage and said simulated load voltage, said voltage difference causing said current mirror to produce said scaled current and voltage, said voltage clamp limiting said scaled voltage, the voltage-limited scaled voltage of said voltage clamp comprising a desired bias voltage; providing a current source; and amplifying in a sense amplifier a first and second low-level logic signals, said second low-level logic signal complementary to said first low-level logic signal, said sense amplifier further having a first and second loads, said bias voltage controlling the current flow of said first and second low-level logic signals in said first and second loads respectively, the voltage corresponding to said controlled current flow in said first and second load comprising amplified first and second high-level controlled logic signals, said first and second high-level logic signals comprising said controlled output swing, said controlled output swing limited to said reference swing voltage.

Claim 37

A method for controlling the output voltage swing of a high speed differential amplifier for amplifying low-level complementary logic signals, said method comprised of the following steps: providing an emitter-coupled differential pair; producing a reference swing voltage; producing a simulated load voltage from a simulated load, said simulated load voltage corresponding to the current flowing in the simulated load; providing a voltage clamp; producing in a current mirror a scaled current and scaled voltage corresponding to the simulated voltage drop across said simulated load, said emitter-coupled pair producing a voltage difference between said reference swing voltage and said simulated load voltage, said voltage difference causing said current mirror to produce said scaled current and voltage, said voltage clamp limiting said scaled voltage, the voltage-limited scaled voltage of said voltage clamp comprising a desired bias voltage; providing a current source; and amplifying in a sense amplifier a first and second low-level logic signals, said second low-level logic signal complementary to said first low-level logic signal, said sense amplifier further having a first and second loads, said bias voltage controlling the current flow of said first and second low-level logic signals in said first and second loads respectively, the voltage corresponding to said controlled current flow in said first and second load comprising amplified first and second high-level controlled logic signals, said first and second high-level logic signals comprising said controlled output swing, said controlled output swing limited to said reference swing voltage.