Semiconductor Integrated circuit device for handling low amplitude signals

Claim 2

A semiconductor integrated circuit device comprising: a first input circuit which receives a low amplitude external clock signal supplied from an external clock unit, said first input circuit including a first differential circuit having a first input which receives the low-amplitude external clock signal and a second input which receives a first reference voltage set to about a middle potential between a high level and a low level of said external clock signal and a current source which is coupled to the first differential circuit, wherein the first differential circuit substantially continuously operates to generate a low-amplitude internal clock signal with an amplitude corresponding to a power supply voltage, and a second input circuit which receives a low-amplitude external input signal inputted synchronously with the low amplitude external clock signal, including a second differential circuit having a first input which receives the low-amplitude external input signal and a second input which receives a second reference voltage set to about a middle potential between a high level and a low level of said low amplitude external input signal, a second current source which is coupled to the second differential circuit, wherein the second input circuit is intermittently operated in accordance with the low-amplitude internal clock signal generated by the first input circuit, wherein the second differential circuit is an input section which generates a low-amplitude internal input signal with an amplitude corresponding to the power supply voltage, and a buffer circuit which samples the low-amplitude internal input signal generated by the input section in accordance with the internal clock signal while the input section is operated and which holds the sampled signal while the input section is not operated.

Claim 3

A semiconductor integrated circuit device comprising a first input circuit and a second input circuit, wherein said first input circuit comprises: a pair of first MOSFETs each having a gate which respectively receive external clock signals being supplied from an outside of said semiconductor integrated circuit device and a first reference voltage, said first reference voltage being substantially a middle potential between a high level and a low level of said external clock signals; a first load circuit coupled to source-drain paths of said pair of first MOSFETs; and a first current source circuit coupled to said source-drain paths of said pair of first MOSFETs, wherein said first input circuit outputs internal clock signals based on said external clock signals, an amplitude of said internal clock signals being larger than an amplitude of said external clock signals, wherein said second input circuit comprises: a pair of second MOSFETs each having a gate which respectively receive input signals being supplied from said outside of said semiconductor integrated circuit device and a second reference voltage, said second reference voltage being substantially a middle potential between a high level and a low level of said input signals; a second load circuit coupled to source-drain paths of said pair of second MOSFETs; and a second current source circuit coupled to said source-drain path of said pair of second MOSFETs, wherein said second input circuit is operated in response to said internal clock signals, and generates internal signals based on said input signals, an amplitude of said internal signals being larger than an amplitude of said input signals.

Claim 4

A semiconductor integrated circuit device comprising a first input circuit and a second input circuit, wherein said first input circuit comprises: a pair of first MOSFETs each having a gate which respectively receive external clock signals being supplied from an outside of said semiconductor integrated circuit device and a first reference voltage, said first reference voltage being substantially a middle potential between a high level and a low level of said external clock signals; a first load circuit coupled to source-drain paths of said pair of first MOSFETs; and a first current source circuit coupled to said source-drain paths of said pair of first MOSFETs, wherein said first input circuit outputs internal clock signals based on said external clock signals, an amplitude of said internal clock signals being larger than an amplitude of said external clock signals, wherein said second input circuit comprises: a pair of second MOSFETs each having a gate which respectively receive input signals being supplied from said outside of said semiconductor integrated circuit device and a second reference voltage, said second reference voltage being substantially a middle potential between a high level and a low level of said input signals; a second load circuit coupled to source-drain paths of said pair of second MOSFETs; and a second current source circuit coupled to said source-drain path of said pair of second MOSFETs, wherein said second input circuit is operated in response to said internal clock signals, and generates internal signals based on said input signals, an amplitude of said internal signals being larger than an amplitude of said input signals.

Claim 5

The semiconductor integrated circuit device according to claim 2, wherein said first current source circuit comprises a MOSFET having a source-drain path coupled to said source-drain paths of said pair of first MOSFETs, and wherein said second current source circuit comprises another MOSFET having a source-drain path coupled to said source-drain paths of said pair of second MOSFETs.

Claim 6

The semiconductor integrated circuit device according to claim 3, wherein the semiconductor integrated circuit device constitutes a synchronous dynamic RAM, wherein said second input circuit is an input circuit for address input signals, or data input signals.

Claim 7

A semiconductor integrated circuit device comprising a first input circuit and a second input circuit, wherein said first input circuit comprises: a pair of first MOSFETs each having a gate which respectively receive external clock signals being supplied from an outside of said semiconductor integrated circuit device and a first reference voltage, said first reference voltage being substantially a middle potential between a high level and a low level of said external clock signals: a first load circuit coupled to source-drain paths of said pair of first MOSFETs; and a first current source circuit coupled to said source-drain paths of said pair of first MOSFETs, wherein said first input circuit outputs internal clock signals based on said external clock signals, an amplitude of said internal clock signals being larger than an amplitude of said external clock signals, wherein said second input circuit includes a latch circuit which receives input signals supplied from the outside of said semiconductor integrated circuit device, a second reference voltage which is substantially a middle potential between a high level and a low level of said input signals, and control signals which responds to said internal clock signals and which latches said input signals in accordance with said control signals, wherein said latch circuit generates internal signals having an amplitude larger than an amplitude of said input signals.

Claim 8

A semiconductor integrated circuit device comprising a first input circuit and a second input circuit, wherein said first input circuit comprises: a pair of first MOSFETs each having a gate which respectively receive external clock signals being supplied from an outside of said semiconductor integrated circuit device and a first reference voltage, said first reference voltage being substantially a middle potential between a high level and a low level of said external clock signals: a first load circuit coupled to source-drain paths of said pair of first MOSFETs; and a first current source circuit coupled to said source-drain paths of said pair of first MOSFETs, wherein said first input circuit outputs internal clock signals based on said external clock signals, an amplitude of said internal clock signals being larger than an amplitude of said external clock signals, wherein said second input circuit includes a latch circuit which receives input signals supplied from the outside of said semiconductor integrated circuit device, a second reference voltage which is substantially a middle potential between a high level and a low level of said input signals, and control signals which responds to said internal clock signals and which latches said input signals in accordance with said control signals, wherein said latch circuit generates internal signals having an amplitude larger than an amplitude of said input signals.

Claim 9

The semiconductor integrated circuit device according to claim 5, further comprising an internal circuit, wherein said internal signals generated by said latch circuit are complementary signals, and wherein said latch circuit has a first terminal and a second terminal for outputting said complementary signals, respectively, and wherein said second input circuit further includes: a pair of signal lines connected to said first terminal and the second terminal of said latch circuit; a first transmission circuit which transmits said input signals and said second reference voltage to each of said pair of signal lines; a second transmission circuit which transmits potentials of said pair of signal lines to said internal circuit; and a precharge circuit which precharges said second reference voltage to said pair of signal lines.

Claim 10

The semiconductor integrated circuit device according to claim 6, wherein said control signals include: a first pulse signal generated in response to a change of said internal clock signals from a first level to a second level; and a second pulse signal which responds to a change of said external clock signals from said first level to said second level, said second pulse signal being generated after said first pulse signal is generated, wherein said first transmission circuit becomes conductive in response to said first pulse signal, wherein said second transmission circuit becomes conductive in response to said second pulse signal.

Claim 11

The semiconductor integrated circuit device according to claim 7, wherein said control signals further include a third pulse signal generated in response to the fact that said external clock signal is set to said first level, and wherein said precharge circuit supplies said second reference voltage to said pair of signal lines responding to said third pulse signal.

Claim 12

The semiconductor integrated circuit device according to claim 7, wherein said first transmission circuit includes: a third terminal which receives said input signals; a fourth terminal which receives said second reference voltage; a first MOSFET having a source-drain path coupled between said third terminal and one of said pair of signal lines and having a gate which receives said first pulse signal: a second MOSFET having a source-drain path coupled between said fourth terminal and the other of said pair of signal lines and having a gate which receives said first pulse signal, wherein said second transmission circuit includes; a third MOSFET having a source-drain path coupled between the one of said pair of signal lines and said internal circuit and having a gate which receives said second pulse signal; and a fourth MOSFET having a source-drain path coupled between the other of said pair of signal lines and said internal circuit and having a gate which receives said second pulse signal, wherein said precharge circuit includes: a fifth MOSFET having a source-drain path coupled between the one of said pair of signal lines and said second reference voltage and having a gate which receives said third pulse signal: a sixth MOSFET having a source-drain path coupled between the other of said pair of signal lines and said second reference voltage and having a gate receiving said third pulse signal; and a seventh MOSFET having a source-drain path coupled between said pair of signal lines and having a gate which receives said third pulse signal, and wherein said latch circuit includes: a first CMOS inverter having an input terminal connected to said first terminal and an output terminal connected to said second terminal; and a second CMOS inverter having an output terminal connected to said input terminal of the first CMOS inverter and an input terminal connected to said output terminal of the first CMOS inverter.

Claim 13

A semiconductor integrated circuit device comprising a first input and a second input circuit, wherein said first input circuit comprising: a pair of first MOSFETs each having a gate which respectively receives external clock signals being supplied from an outside of said semiconductor integrated circuit device and a first reference voltage, said first reference voltage being substantially a middle potential between a high level and a low level of said external clock signals; a first load circuit coupled to source-drain paths of said pair of first MOSFETs; and a first current source circuit coupled to said source-drain paths of said pair of first MOSFETs, wherein said first input circuit outputs internal clock signals based on said external clock signals, an amplitude of said internal clock signals being larger than an amplitude of said external clock signals, wherein said second input circuit receives input signals supplied from said outside of the semiconductor integrated circuit device, a second reference voltage which is substantially a middle potential between a high level and a low level of said input signals, and said internal clock signals and generates internal signals having an amplitude larger than an amplitude of said input signals, and wherein said second input circuit is operated in response to said internal clock signals.

Claim 14

A semiconductor integrated circuit device comprising a first input and a second input circuit, wherein said first input circuit comprising: a pair of first MOSFETs each having a gate which respectively receives external clock signals being supplied from an outside of said semiconductor integrated circuit device and a first reference voltage, said first reference voltage being substantially a middle potential between a high level and a low level of said external clock signals; a first load circuit coupled to source-drain paths of said pair of first MOSFETs; and a first current source circuit coupled to said source-drain paths of said pair of first MOSFETs, wherein said first input circuit outputs internal clock signals based on said external clock signals, an amplitude of said internal clock signals being larger than an amplitude of said external clock signals, wherein said second input circuit receives input signals supplied from said outside of the semiconductor integrated circuit device, a second reference voltage which is substantially a middle potential between a high level and a low level of said input signals, and said internal clock signals and generates internal signals having an amplitude larger than an amplitude of said input signals, and wherein said second input circuit is operated in response to said internal clock signals.

Claim 15

The semiconductor integrated circuit device according to claim 10, wherein said second input circuit includes: a pair of second MOSFETs each having a gate which respectively receives said input signals and said second reference voltage; a second load circuit coupled to source-drain paths of said pair of second MOSFETs; and a second current source circuit coupled to said source-drain paths of said pair of second MOSFETs.

Claim 16

The semiconductor integrated circuit device according to claim 11, wherein said second current source circuit includes a MOSFET which is turned on in response to said internal clock signals.