TTL to CMOS buffer circuit

Claim 2

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; and a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source, wherein the second current mirror circuit is not connected in series with the first current mirror circuit.

Claim 3

A buffer circuit according to claim 1, wherein said first current mirror circuit includes a fifth MOS transistor of the second conductivity type whose drain and gate are connected to the drain of said first MOS transistor and whose source is connected to said second potential supplying source and a sixth MOS transistor of the second conductivity type having a drain connected to the drain of said second MOS transistor, a source connected to said second potential supplying source and a gate connected to the gate of said fifth MOS transistor.

Claim 4

A buffer circuit according to claim 1, wherein said second current mirror circuit includes a fifth MOS transistor of the first conductivity type whose source is connected to said first potential supplying source and whose drain and gate are connected to the drain of said third MOS transistor and a sixth MOS transistor of the first conductivity type having a source connected to said first potential supplying source, a drain connected to the drain of said fourth MOS transistor and a gate connected to the gate of said seventh MOS transistor.

Claim 5

A buffer circuit according to claim 1, wherein the voltage of said second potential supplying source is at a ground potential level, the voltage of said first potential supplying source is set at a power source voltage level higher than the ground potential level, and the reference potential is set at a potential level between the power source voltage level and ground potential level.

Claim 6

A buffer circuit according to claim 1, wherein said input signal is set at a TTL level and said output signal is set at a CMOS logic level.

Claim 7

A buffer circuit according to claim 1, wherein said MOS transistor of the first conductivity type is a P-channel MOS transistor and said MOS transistor of the second conductivity type is an N-channel MOS transistor.

Claim 8

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first switching means which is connected between said first potential supplying source and the sources of said first and second MOS transistors and whose conduction state is controlled in response to a control signal; and second switching means which is connected between said second potential supplying source and the sources of said third and fourth MOS transistors and whose conduction state is controlled in response to the control signal.

Claim 9

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first switching means which is connected between said first potential supplying source and the sources of said first and second MOS transistors and whose conduction state is controlled in response to a control signal; and second switching means which is connected between said second potential supplying source and the sources of said third and fourth MOS transistors and whose conduction state is controlled in response to the control signal.

Claim 10

A buffer circuit according to claim 7, wherein said first switching means includes a MOS transistor of the first conductivity type and said second switching means includes a MOS transistor of the second conductivity type.

Claim 11

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first switching means which is connected between said first potential supplying source and said second current mirror circuit and whose conduction state is controlled in response to a control signal; and second switching means which is connected between said second potential supplying source and said first current mirror circuit and whose conduction state is controlled in response to the control signal.

Claim 12

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first switching means which is connected between said first potential supplying source and said second current mirror circuit and whose conduction state is controlled in response to a control signal; and second switching means which is connected between said second potential supplying source and said first current mirror circuit and whose conduction state is controlled in response to the control signal.

Claim 13

A buffer circuit according to claim 9, wherein said first switching means includes a MOS transistor of the first conductivity type and said second switching means includes a MOS transistor of the second conductivity type.

Claim 14

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first switching means which is connected between said first potential supplying source and the sources of said first and second MOS transistors and whose conduction state is controlled in response to a control signal; and second switching means which is connected between said first potential supplying source and said second current mirror circuit and whose conduction state is controlled in response to the control signal.

Claim 15

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first switching means which is connected between said first potential supplying source and the sources of said first and second MOS transistors and whose conduction state is controlled in response to a control signal; and second switching means which is connected between said first potential supplying source and said second current mirror circuit and whose conduction state is controlled in response to the control signal.

Claim 16

A buffer circuit according to claim 11, wherein said first and second switching means each include a MOS transistor of the first conductivity type.

Claim 17

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first switching means which is connected between said second potential supplying source and said first current mirror circuit and whose conduction state is controlled in response to a control signal; and second switching means which is connected between said second potential supplying source and the sources of said third and fourth MOS transistors and whose conduction state is controlled in response to the control signal.

Claim 18

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first switching means which is connected between said second potential supplying source and said first current mirror circuit and whose conduction state is controlled in response to a control signal; and second switching means which is connected between said second potential supplying source and the sources of said third and fourth MOS transistors and whose conduction state is controlled in response to the control signal.

Claim 19

A buffer circuit according to claim 13, wherein said first and second switching means each include a MOS transistor of the second conductivity type.

Claim 20

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first switching means which is connected between said first potential supplying source and the sources of said first and second MOS transistors and whose conduction state is controlled in response to a control signal; second switching means which is connected between said second potential supplying source and said first current mirror circuit and whose conduction state is controlled in response to an inverted signal of the control signal; third switching means which is connected between said first potential supplying source and said second current mirror circuit and whose conduction state is controlled in response to the control signal; and fourth switching means which is connected between said second potential supplying source and the sources of said third and fourth MOS transistors and whose conduction state is controlled in response to the inverted signal of the control signal.

Claim 21

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first switching means which is connected between said first potential supplying source and the sources of said first and second MOS transistors and whose conduction state is controlled in response to a control signal; second switching means which is connected between said second potential supplying source and said first current mirror circuit and whose conduction state is controlled in response to an inverted signal of the control signal; third switching means which is connected between said first potential supplying source and said second current mirror circuit and whose conduction state is controlled in response to the control signal; and fourth switching means which is connected between said second potential supplying source and the sources of said third and fourth MOS transistors and whose conduction state is controlled in response to the inverted signal of the control signal.

Claim 22

A buffer circuit according to claim 15, wherein said first and third switching means each include a MOS transistor of the first conductivity type and said second and fourth switching means each include a MOS transistor of the second conductivity type.

Claim 23

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first load means connected between said first potential supplying source and the sources of said first and second MOS transistors; and second load means connected between said second potential supplying source and the sources of said third and fourth MOS transistors.

Claim 24

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first load means connected between said first potential supplying source and the sources of said first and second MOS transistors; and second load means connected between said second potential supplying source and the sources of said third and fourth MOS transistors.

Claim 25

A buffer circuit according to claim 17, wherein said first load means includes a MOS transistor of the first conductivity type having a source connected to said first potential supplying source, a drain connected to the sources of said first and second MOS transistors and a gate connected to said second potential supplying source and said second load means includes a MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the sources of said third and fourth MOS transistors and a gate connected to said first potential supplying source.

Claim 26

A buffer circuit according to claim 17, wherein said first load means includes a first resistor connected at one end to said first potential supplying source and connected at the other end to the sources of said first and second MOS transistors and said second load means includes a second resistor connected at one end to said second potential supplying source and connected at the other end to the sources of said third and fourth MOS transistors.

Claim 27

A buffer circuit according to claim 17, wherein said first load means includes a first diode having an anode connected to said first potential supplying source and a cathode connected to the sources of said first and second MOS transistors and said second load means includes a second diode having a cathode connected to second potential supplying source and an anode connected to the sources of said third and fourth MOS transistors.

Claim 28

A buffer circuit according to claim 17, wherein said first load means includes a MOS transistor of the first conductivity type having a source connected to said first potential supplying source, a drain connected to the sources of said first and second MOS transistors and a gate connected to the drain of said first MOS transistor and said second load means includes a MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the source of said third and fourth MOS transistors and a gate connected to the drain of said third MOS transistor.

Claim 29

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first load means connected between said first potential supplying source and said second current mirror circuit; and second load means connected between said second potential supplying source and said first current mirror circuit.

Claim 30

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first load means connected between said first potential supplying source and said second current mirror circuit; and second load means connected between said second potential supplying source and said first current mirror circuit.

Claim 31

A buffer circuit according to claim 22, wherein said first load means includes a MOS transistor of the first conductivity type having a source connected to said first potential supplying source, a drain connected to said second current mirror circuit and a gate connected to said second potential supplying source and said second load means includes a MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to said first current mirror circuit and a gate connected to said first potential supplying source.

Claim 32

A buffer circuit according to claim 22, wherein said first load means includes a first resistor connected at one end to said first potential supplying source and connected at the other end to said second current mirror circuit and said second load means includes a second resistor connected at one end to said second potential supplying source and connected at the other end to said first current mirror circuit.

Claim 33

A buffer circuit according to claim 22, wherein said first load means includes a first diode having an anode connected to said first potential supplying source and a cathode connected to said second current mirror circuit and said second load means includes a second diode having an anode connected to said first mirror circuit and a cathode connected to said second potential supplying source.

Claim 34

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first load means connected between said first potential supplying source and the sources of said first and second MOS transistors; second load means connected between said second potential supplying source and said first current mirror circuit; third load means connected between said first potential supplying source and said second current mirror circuit; and fourth load means connected between said second potential supplying source and the sources of said third and fourth MOS transistors.

Claim 35

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first load means connected between said first potential supplying source and the sources of said first and second MOS transistors; second load means connected between said second potential supplying source and said first current mirror circuit; third load means connected between said first potential supplying source and said second current mirror circuit; and fourth load means connected between said second potential supplying source and the sources of said third and fourth MOS transistors.

Claim 36

A buffer circuit according to claim 26, wherein said first load means includes a first load MOS transistor of the first conductivity type having a source connected to said first potential supplying source, a drain connected to the sources of said first and second MOS transistors and a gate connected to said second potential supplying source; said second load means includes a second load MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to said first current mirror circuit and a gate connected to said first potential supplying source; said third load means includes a third load MOS transistor of the first conductivity type having a source connected to said first potential supplying source, a drain connected to said second current mirror circuit and a gate connected to said second potential supplying source; and said fourth load means includes a fourth load MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the sources of said third and fourth MOS transistors and a gate connected to said first potential supplying source.

Claim 37

A buffer circuit according to claim 26, wherein said first load means includes a first resistor connected at one end to said first potential supplying source and connected at the other end to the sources of said first and second MOS transistors; said second load means includes a second resistor connected at one end to said second potential supplying source and connected at the other end to said first current mirror circuit; said third load means includes a third resistor connected at one end to said first potential supplying source and connected at the other end to said second current mirror circuit; and said fourth load means includes a second resistor connected at one end to said second potential supplying source and connected at the other end to the sources of said third and fourth MOS transistors.

Claim 38

A buffer circuit according to claim 26, wherein said first load means includes a first diode having an anode connected to said first potential supplying source and a cathode connected to the sources of said first and second MOS transistors; said second load means includes a second diode having an anode connected to said first current mirror circuit and a cathode connected to said second potential supplying source; said third load means includes a third diode having an anode connected to said first potential supplying source and a cathode connected to said second current mirror circuit; and said fourth load means includes a fourth diode having a cathode connected to said first potential supplying source and an anode connected to the sources of said third and fourth MOS transistors.

Claim 39

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first switching means connected between the drains of said first and second MOS transistors and said first current mirror circuit; and second switching means connected between said second current mirror circuit and the drains of said third and fourth MOS transistors.

Claim 40

A buffer circuit comprising: a first potential supplying source; a first MOS transistor of a first conductivity type having a source connected to said first potential supplying source and a gate supplied with a reference potential; a second MOS transistor of the first conductivity type having a source connected to said first potential supplying source and a gate supplied with an input signal; a second potential supplying source; a first current mirror circuit including MOS transistors of a second conductivity type and connected between the drains of said first and second MOS transistors and said second potential supplying source; a third MOS transistor of the second conductivity type having a source connected to said second potential supplying source and a gate supplied with the reference potential; a fourth MOS transistor of the second conductivity type having a source connected to said second potential supplying source, a drain connected to the drain of said second MOS transistor and a gate supplied with the input signal, an output signal being derived from a connection node between the drains of said second and fourth MOS transistors; a second current mirror circuit including MOS transistors of the first conductivity type and connected between the drains of said third and fourth MOS transistors and said first potential supplying source; first switching means connected between the drains of said first and second MOS transistors and said first current mirror circuit; and second switching means connected between said second current mirror circuit and the drains of said third and fourth MOS transistors.

Claim 41

A buffer circuit according to claim 30, wherein said first switching means includes a first switching MOS transistor whose drain is connected to the drain of said first MOS transistor and whose source is connected to the gate of one of the MOS transistors constituting said first current mirror circuit and whose conduction state is controlled by a control signal and a second switching MOS transistor whose drain is connected to the drain of said second MOS transistor and whose source is connected to the drain of the other of the MOS transistors constituting said first current mirror circuit and whose conduction state is controlled by the control signal; and said second switching means includes a third switching MOS transistor whose source is connected to the drain of said third MOS transistor and whose drain is connected to the drain of one of the MOS transistors constituting said second current mirror circuit and whose conduction state is controlled by a control signal and a fourth switching MOS transistor whose source is connected to the drain of said fourth MOS transistor and whose drain is connected to the gate of the other of the MOS transistors constituting said second current mirror circuit and whose conduction state is controlled by the control signal.