Semiconductor device including a plurality of input buffer circuits receiving the same control signal

Claim 2

A semiconductor device comprising: a semiconductor chip including plurality of bonding pads formed on an insulating layer on a surface of a semiconductor substrate, each bonding pad receiving the same control signal, a plurality of input buffer circuits provided corresponding to said plurality of bonding pads and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node thereof, a plurality of input interconnection layers provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each input interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, and an output interconnection layer of a metal wire formed on the insulating layer on the surface of said semiconductor substrate for electrically connecting output nodes of said plurality of input buffer circuits, a lead terminal provided corresponding to said plurality of bonding pads for receiving said control signal, and a plurality of metal wires provided corresponding to said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 3

A semiconductor device comprising: a semiconductor chip including a plurality of bonding pad groups formed on an insulating layer on a surface of a semiconductor substrate, each bonding group including a plurality of bonding pads to which the same control signal is applied, a plurality of input buffer circuits provided corresponding to said plurality of bonding pad groups and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal wire provided corresponding to said plurality of bonding pad groups and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting said plurality of bonding pads of a corresponding bonding pad group with an input node of a corresponding input buffer circuit, lead terminals provided corresponding to said plurality of bonding pad groups for receiving said control signal, and a plurality of metal wires provided corresponding to said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 4

A semiconductor device comprising: a semiconductor chip including a plurality of bonding pad groups formed on an insulating layer on a surface of a semiconductor substrate, each bonding group including a plurality of bonding pads to which the same control signal is applied, a plurality of input buffer circuits provided corresponding to said plurality of bonding pad groups and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal wire provided corresponding to said plurality of bonding pad groups and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting said plurality of bonding pads of a corresponding bonding pad group with an input node of a corresponding input buffer circuit, lead terminals provided corresponding to said plurality of bonding pad groups for receiving said control signal, and a plurality of metal wires provided corresponding to said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 5

A semiconductor device comprising: a semiconductor chip including a plurality of bonding pad groups formed on an insulating layer on a surface of a semiconductor substrate, each bonding pad group including a plurality of bonding pads to which the same control signal is applied, a plurality of input buffer circuits provided corresponding to the plurality of bonding pads of said plurality of bonding pad groups and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, a plurality of lead terminals provided corresponding to said plurality of bonding pad groups, each lead terminal receiving said control signal, and a plurality of metal wire groups provided corresponding to said plurality of bonding pad groups, and each group including a plurality of metal wires, each metal wire electrically connecting a corresponding bonding pad of a corresponding bonding pad group with a corresponding lead terminal, wherein said semiconductor chip further includes an output interconnection layer formed on the insulating layer on the surface of said semiconductor substrate for electrically connecting output nodes of said plurality of input buffer circuits.

Claim 6

A semiconductor device comprising: a semiconductor chip including a plurality of bonding pad groups formed on an insulating layer on a surface of a semiconductor substrate, each bonding pad group including a plurality of bonding pads to which the same control signal is applied, a plurality of input buffer circuits provided corresponding to the plurality of bonding pads of said plurality of bonding pad groups and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, a plurality of lead terminals provided corresponding to said plurality of bonding pad groups, each lead terminal receiving said control signal, and a plurality of metal wire groups provided corresponding to said plurality of bonding pad groups, and each group including a plurality of metal wires, each metal wire electrically connecting a corresponding bonding pad of a corresponding bonding pad group with a corresponding lead terminal, wherein said semiconductor chip further includes an output interconnection layer formed on the insulating layer on the surface of said semiconductor substrate for electrically connecting output nodes of said plurality of input buffer circuits.

Claim 7

A semiconductor device comprising: a semiconductor chip including a plurality of bonding pad groups formed on an insulating layer on a surface of a semiconductor substrate, each bonding pad group including a plurality of bonding pads to which the same control signal is applied, a plurality of input buffer circuits provided corresponding to said plurality of bonding pad groups and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of bonding pad groups and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting the plurality of bonding pads of a corresponding bonding pad group with an input node of a corresponding input buffer circuit, a plurality of lead terminals provided corresponding to said plurality of bonding pad groups, each lead terminal receiving said control signal, and a plurality of metal wire groups provided corresponding to said plurality of bonding pad groups, and each group including a plurality of metal wires, each metal wire electrically connecting a corresponding bonding pad of a corresponding bonding pad group with a corresponding lead terminal.

Claim 8

A semiconductor device comprising: a semiconductor chip including a plurality of bonding pad groups formed on an insulating layer on a surface of a semiconductor substrate, each bonding pad group including a plurality of bonding pads to which the same control signal is applied, a plurality of input buffer circuits provided corresponding to said plurality of bonding pad groups and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of bonding pad groups and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting the plurality of bonding pads of a corresponding bonding pad group with an input node of a corresponding input buffer circuit, a plurality of lead terminals provided corresponding to said plurality of bonding pad groups, each lead terminal receiving said control signal, and a plurality of metal wire groups provided corresponding to said plurality of bonding pad groups, and each group including a plurality of metal wires, each metal wire electrically connecting a corresponding bonding pad of a corresponding bonding pad group with a corresponding lead terminal.

Claim 9

A semiconductor device comprising: a semiconductor chip including a rectangular semiconductor substrate having longer sides and shorter sides, a plurality of bonding pads formed on an insulating layer on a surface of said semiconductor substrate, each bonding pad receiving the same control signal, a plurality of input buffer circuits provided corresponding to said plurality of bonding pads and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, a lead terminal provided corresponding to said plurality of bonding pads, and including a lead segment having one end receiving externally applied said control signal, and a connection segment formed integral with the other end of said lead segment, and parallel to the longer side of said semiconductor substrate, and a plurality of metal wires provided corresponding to said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 10

A semiconductor device comprising: a semiconductor chip including a rectangular semiconductor substrate having longer sides and shorter sides, a plurality of bonding pads formed on an insulating layer on a surface of said semiconductor substrate, each bonding pad receiving the same control signal, a plurality of input buffer circuits provided corresponding to said plurality of bonding pads and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, a lead terminal provided corresponding to said plurality of bonding pads, and including a lead segment having one end receiving externally applied said control signal, and a connection segment formed integral with the other end of said lead segment, and parallel to the longer side of said semiconductor substrate, and a plurality of metal wires provided corresponding to said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 11

The semiconductor device according to claim 5, wherein said semiconductor chip further includes an output interconnection layer of a metal layer formed on the insulating layer on the surface of said semiconductor substrate for electrically connecting output nodes of said plurality of input buffer circuits.

Claim 12

The semiconductor device according to claim 6, wherein said lead segment of said lead terminal includes first and second sections in close proximity to respective shorter sides of said semiconductor substrate for receiving externally applied said control signal at one end, and wherein said connection segment of said lead terminal is located between the other ends of said first and second sections of said lead segment.

Claim 13

The semiconductor device according to claim 5, wherein said lead segment of said lead terminal includes first and second sections in close proximity to respective shorter sides of said semiconductor substrate for receiving externally applied said control signal at one end, and wherein said connection segment of said lead terminal is located between the other ends of said first and second sections of said lead segment.

Claim 14

The semiconductor device according to claim 5, wherein said plurality of bonding pads are arranged along a center line parallel to a longer side of said semiconductor substrate, such that a bonding pad to which another control signal is applied is provided between at least two bonding pads.

Claim 15

The semiconductor device according to claim 9, wherein said lead segment of said lead terminal includes first and second sections in close proximity to respective shorter sides of said semiconductor substrate for receiving externally applied said control signal at one end, and wherein said connection segment of said lead terminal is located between the other ends of said first and second sections of said lead segment.

Claim 16

The semiconductor device according to claim 9, wherein said semiconductor chip further includes an output interconnection layer of a metal layer formed on the insulating layer on the surface of said semiconductor substrate for electrically connecting output nodes of said plurality of input buffer circuits.

Claim 17

A semiconductor device comprising: a semiconductor chip including a plurality of bonding pad groups formed on an insulating layer on a surface of a semiconductor substrate, each bonding pad group including a plurality of bonding pads receiving the same control signal, a plurality of input buffer circuits provided corresponding to said plurality of bonding pad groups and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of bonding pad groups and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting said plurality of bonding pads of a corresponding bonding pad group with an input node of a corresponding input buffer circuit, a lead terminal provided corresponding to the plurality of bonding pads of said bonding pad groups, and including a lead segment for receiving externally applied said control signal at one end, and a connection segment formed integral with the other end of said lead segment, and parallel to the longer side of said semiconductor substrate, and a plurality of metal wires provided corresponding to said plurality of bonding pads of said plurality of bonding pad groups, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 18

A semiconductor device comprising: a semiconductor chip including a plurality of bonding pad groups formed on an insulating layer on a surface of a semiconductor substrate, each bonding pad group including a plurality of bonding pads receiving the same control signal, a plurality of input buffer circuits provided corresponding to said plurality of bonding pad groups and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of bonding pad groups and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting said plurality of bonding pads of a corresponding bonding pad group with an input node of a corresponding input buffer circuit, a lead terminal provided corresponding to the plurality of bonding pads of said bonding pad groups, and including a lead segment for receiving externally applied said control signal at one end, and a connection segment formed integral with the other end of said lead segment, and parallel to the longer side of said semiconductor substrate, and a plurality of metal wires provided corresponding to said plurality of bonding pads of said plurality of bonding pad groups, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 19

The semiconductor device according to claim 12, wherein said lead segment of said lead terminal includes first and second sections in close proximity to respective shorter sides of said semiconductor substrate for receiving externally applied said control signal at one end, and wherein said connection segment of said lead terminal is located between the other ends of said first and second sections of said lead segment.

Claim 20

A semiconductor device comprising: a semiconductor chip including a rectangular semiconductor substrate having longer sides and shorter sides, a plurality of bonding pads formed on an insulating layer on a surface of said semiconductor substrate, including a right side row and a left side row of bonding pads arranged along a center line parallel to the longer side of said semiconductor substrate, and having the same control signal applied to a predetermined number of bonding pads of said right side row and a predetermined number of bonding pads of said left side row, a plurality of input buffer circuits provided corresponding to said predetermined number of bonding pads of right side row and left side row and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, a lead terminal provided corresponding to said predetermined number of said right side row and left side row of bonding pads, and including a lead segment for receiving externally applied said control signal at one end, and a connection segment formed integral with the other end of said lead segment, parallel to the longer side of said semiconductor substrate, and located between said right side row and left side row of bonding pads, and a plurality of metal wires provided corresponding to said predetermined number of bonding pads of the right side row and the left side row, each metal wire electrically connecting a corresponding bonding pad and said connection segment of said lead terminal.

Claim 21

A semiconductor device comprising: a semiconductor chip including a rectangular semiconductor substrate having longer sides and shorter sides, a plurality of bonding pads formed on an insulating layer on a surface of said semiconductor substrate, including a right side row and a left side row of bonding pads arranged along a center line parallel to the longer side of said semiconductor substrate, and having the same control signal applied to a predetermined number of bonding pads of said right side row and a predetermined number of bonding pads of said left side row, a plurality of input buffer circuits provided corresponding to said predetermined number of bonding pads of right side row and left side row and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, a lead terminal provided corresponding to said predetermined number of said right side row and left side row of bonding pads, and including a lead segment for receiving externally applied said control signal at one end, and a connection segment formed integral with the other end of said lead segment, parallel to the longer side of said semiconductor substrate, and located between said right side row and left side row of bonding pads, and a plurality of metal wires provided corresponding to said predetermined number of bonding pads of the right side row and the left side row, each metal wire electrically connecting a corresponding bonding pad and said connection segment of said lead terminal.

Claim 22

The semiconductor device according to claim 14, wherein said lead segment of said lead terminal includes first and second sections in close proximity to respective shorter sides of said semiconductor substrate for receiving externally applied said control signal at one end, and wherein said connection segment of said lead terminal is located between the other ends of said first and second sections of said lead segment.

Claim 23

The semiconductor device according to claim 15, wherein said semiconductor chip further includes an output interconnection layer formed on the insulating layer on the surface of said semiconductor substrate for electrically connecting output nodes of said plurality of input buffer circuits.

Claim 24

The semiconductor device according to claim 14, wherein said semiconductor chip further includes an output interconnection layer formed on the insulating layer on the surface of said semiconductor substrate for electrically connecting output nodes of said plurality of input buffer circuits.

Claim 25

A semiconductor device comprising: a semiconductor chip including a rectangular semiconductor substrate having longer sides and shorter sides, a plurality of bonding pads formed on an insulating layer on a surface of said semiconductor substrate arranged along a center line parallel to the shorter side of said semiconductor substrate, each bonding pad receiving the same control signal, a plurality of input buffer circuits provided corresponding to said plurality of bonding pads and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, a lead terminal provided corresponding to said plurality of bonding pads for receiving said control signal, said lead terminal being provided at a center line parallel to the longer side of the semiconductor chip, and a plurality of metal wires provided corresponding to each of said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 26

A semiconductor device comprising: a semiconductor chip including a rectangular semiconductor substrate having longer sides and shorter sides, a plurality of bonding pads formed on an insulating layer on a surface of said semiconductor substrate arranged along a center line parallel to the shorter side of said semiconductor substrate, each bonding pad receiving the same control signal, a plurality of input buffer circuits provided corresponding to said plurality of bonding pads and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, a lead terminal provided corresponding to said plurality of bonding pads for receiving said control signal, said lead terminal being provided at a center line parallel to the longer side of the semiconductor chip, and a plurality of metal wires provided corresponding to each of said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 27

The semiconductor device according to claim 18, wherein said semiconductor chip further includes an output interconnection layer of a metal layer formed on the insulating layer on the surface of said semiconductor substrate for electrically connecting output nodes of said plurality of input buffer circuits.

Claim 28

The semiconductor device according to claim 18, wherein said lead terminal includes a lead segment for receiving externally applied said control signal at one end, and a connection segment formed integral with the other end of said lead segment, located parallel to the longer side of said semiconductor substrate and at a center portion of said semiconductor substrate.

Claim 29

The semiconductor device according to claim 20, wherein said semiconductor chip further includes an output interconnection layer formed on the insulating layer on the surface of said semiconductor substrate for electrically connecting output nodes of said plurality of input buffer circuits.

Claim 30

The semiconductor device according to claim 20, wherein said lead segment of said lead terminal includes first and second sections in close proximity to respective shorter sides of said semiconductor substrate for receiving externally applied said control signal at one end, and wherein said connection segment of said lead terminal is located between the other ends of said first and second sections of said lead segment.

Claim 31

The semiconductor device according to claim 22, wherein said semiconductor chip further includes an output interconnection layer formed on the insulating layer on the surface of said semiconductor substrate for electrically connecting output nodes of said plurality of input buffer circuits.

Claim 32

A semiconductor device comprising: a semiconductor chip including a rectangular semiconductor substrate having shorter sides and longer sides, a plurality of bonding pads formed on an insulating layer on a surface of said semiconductor substrate, and including a longer side row and a shorter side row of bonding pads arranged along a center line parallel to the longer side of said semiconductor substrate and a center line parallel to the shorter side of said semiconductor substrate, the same control signal being applied to a predetermined number of bonding pads of said longer side row and a predetermined number of bonding pads of said shorter side row, a plurality of input buffer circuits provided corresponding to said predetermined number of bonding pads of said longer side row and shorter side row and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, a lead terminal receiving said control signal, provided corresponding to said predetermined number of bonding pads in said longer side row and shorter side row of bonding pads, said lead terminal being provided at a center line parallel to the longer side of the semiconductor chip, a plurality of metal wires provided corresponding to said predetermined number of bonding pads of said longer side row and shorter side row of said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 33

A semiconductor device comprising: a semiconductor chip including a rectangular semiconductor substrate having shorter sides and longer sides, a plurality of bonding pads formed on an insulating layer on a surface of said semiconductor substrate, and including a longer side row and a shorter side row of bonding pads arranged along a center line parallel to the longer side of said semiconductor substrate and a center line parallel to the shorter side of said semiconductor substrate, the same control signal being applied to a predetermined number of bonding pads of said longer side row and a predetermined number of bonding pads of said shorter side row, a plurality of input buffer circuits provided corresponding to said predetermined number of bonding pads of said longer side row and shorter side row and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, a lead terminal receiving said control signal, provided corresponding to said predetermined number of bonding pads in said longer side row and shorter side row of bonding pads, said lead terminal being provided at a center line parallel to the longer side of the semiconductor chip, a plurality of metal wires provided corresponding to said predetermined number of bonding pads of said longer side row and shorter side row of said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 34

The semiconductor device according to claim 24, wherein said lead terminal includes a lead segment for receiving externally applied said control signal at one end, and a connection segment formed integral with the other end of said lead terminal and located parallel to the longer side of said semiconductor substrate and at a central portion of said semiconductor substrate.

Claim 35

The semiconductor device according to claim 25, wherein said lead segment of said lead terminal includes first and second sections in close proximity to respective shorter sides of said semiconductor substrate for receiving externally applied said control signal at one end, and wherein said connection segment of said lead terminal is located between the other ends of said first and second sections of said lead terminal.

Claim 36

The semiconductor device according to claim 26, wherein said semiconductor chip further includes an output interconnection layer formed of a metal layer on the insulating layer of said surface of said semiconductor substrate for electrically connecting output nodes of said plurality of input buffer circuits.

Claim 37

A semiconductor device comprising: a semiconductor chip including a rectangular semiconductor substrate having longer sides and shorter sides, a plurality of bonding pads formed on an insulating layer on a surface of said semiconductor substrate, and arranged at four corners of said semiconductor substrate, each receiving the same control signal, a plurality of input buffer circuits provided corresponding to said plurality of bonding pads and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, a lead terminal provided corresponding to said plurality of bonding pads, and including a lead segment having first and second sections in close proximity to respective shorter sides of said semiconductor substrate for receiving externally applied said control signal at one end, and a connection segment formed integral with said lead segment and located between the other ends of said first and second sections, and a plurality of metal wires provided corresponding to said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 38

A semiconductor device comprising: a semiconductor chip including a rectangular semiconductor substrate having longer sides and shorter sides, a plurality of bonding pads formed on an insulating layer on a surface of said semiconductor substrate, and arranged at four corners of said semiconductor substrate, each receiving the same control signal, a plurality of input buffer circuits provided corresponding to said plurality of bonding pads and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, a lead terminal provided corresponding to said plurality of bonding pads, and including a lead segment having first and second sections in close proximity to respective shorter sides of said semiconductor substrate for receiving externally applied said control signal at one end, and a connection segment formed integral with said lead segment and located between the other ends of said first and second sections, and a plurality of metal wires provided corresponding to said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal.

Claim 39

A semiconductor device comprising: a first semiconductor chip including a first bonding pad formed on an insulating layer on a surface of a first semiconductor substrate for receiving a control signal, a first input buffer provided corresponding to said first bonding pad and formed on the surface of said first semiconductor substrate for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a first interconnection of a metal layer provided corresponding to said first input buffer circuit and formed on the insulating layer on the surface of said first semiconductor substrate for electrically connecting an input node of said first input buffer circuit with a corresponding bonding pad; and a second semiconductor chip including a second bonding pad formed on an insulating layer on a surface of a second semiconductor substrate for receiving said control signal, a second input buffer circuit provided corresponding to said second bonding pad and formed on the surface of said semiconductor substrate for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a second interconnection of a metal layer provided corresponding to said second input buffer circuit and formed on the insulating layer on the surface of said second semiconductor substrate for electrically connecting an input node of said second input buffer circuit with a corresponding bonding pad; a lead terminal provided corresponding to said first and second bonding pads for receiving said control signal; first and second metal wires provided corresponding to said first and second bonding pads, respectively, each metal wire electrically connecting a corresponding bonding pad with said lead terminal; and a metal output interconnection layer formed for electrically connecting output nodes of said first and second input buffer circuits.

Claim 40

A semiconductor device comprising: a first semiconductor chip including a first bonding pad formed on an insulating layer on a surface of a first semiconductor substrate for receiving a control signal, a first input buffer provided corresponding to said first bonding pad and formed on the surface of said first semiconductor substrate for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a first interconnection of a metal layer provided corresponding to said first input buffer circuit and formed on the insulating layer on the surface of said first semiconductor substrate for electrically connecting an input node of said first input buffer circuit with a corresponding bonding pad; and a second semiconductor chip including a second bonding pad formed on an insulating layer on a surface of a second semiconductor substrate for receiving said control signal, a second input buffer circuit provided corresponding to said second bonding pad and formed on the surface of said semiconductor substrate for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a second interconnection of a metal layer provided corresponding to said second input buffer circuit and formed on the insulating layer on the surface of said second semiconductor substrate for electrically connecting an input node of said second input buffer circuit with a corresponding bonding pad; a lead terminal provided corresponding to said first and second bonding pads for receiving said control signal; first and second metal wires provided corresponding to said first and second bonding pads, respectively, each metal wire electrically connecting a corresponding bonding pad with said lead terminal; and a metal output interconnection layer formed for electrically connecting output nodes of said first and second input buffer circuits.

Claim 41

A semiconductor device comprising: a semiconductor chip including a plurality of bonding pads formed on an insulating layer on a surface of a semiconductor substrate and formed along the periphery of said semiconductor substrate, each bonding pad receiving the same control signal, a plurality of input buffer circuits provided corresponding to said plurality of bonding pads and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, lead terminal means provided corresponding to said plurality of bonding pads for receiving said control signal, a plurality of metal wires provided corresponding to said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal means, and a metal output interconnection layer formed on the insulating layer on the surface of said semiconductor substrate for electrically connecting the output nodes of said plurality of input buffer circuits.

Claim 42

A semiconductor device comprising: a semiconductor chip including a plurality of bonding pads formed on an insulating layer on a surface of a semiconductor substrate and formed along the periphery of said semiconductor substrate, each bonding pad receiving the same control signal, a plurality of input buffer circuits provided corresponding to said plurality of bonding pads and formed on the surface of said semiconductor substrate, each for receiving said control signal at an input node and providing a signal according to said control signal to an output node, and a plurality of interconnection layers of a metal layer provided corresponding to said plurality of input buffer circuits and formed on the insulating layer on the surface of said semiconductor substrate, each interconnection layer electrically connecting an input node of a corresponding input buffer circuit with a corresponding bonding pad, lead terminal means provided corresponding to said plurality of bonding pads for receiving said control signal, a plurality of metal wires provided corresponding to said plurality of bonding pads, each metal wire electrically connecting a corresponding bonding pad with said lead terminal means, and a metal output interconnection layer formed on the insulating layer on the surface of said semiconductor substrate for electrically connecting the output nodes of said plurality of input buffer circuits.

Claim 43

The semiconductor device according to claim 30, wherein said lead terminal means comprises a first lead terminal provided corresponding to a predetermined number of said plurality of bonding pads, and a second lead terminal provided corresponding to said plurality of bonding pads excluding said predetermined number of bonding pads.