US5799207A — Non-blocking peripheral access architecture havin…

Claim 1

Independent Claim 130 words

In a computer system comprising a master, a memory, an I/O expansion bus, an I/O transfer interconnection not connected to the expansion bus, an I/O device connected to the I/O expansion bus and the I/O transfer interconnection, and a register configured to indicate one of said I/O expansion bus and said I/O transfer interconnection for transfers between said master and said I/O device, a transfer process comprising the steps of: (a) selecting the I/O device to the I/O expansion bus for performing a transfer on a first path between said I/O device and said memory; and (b) selecting the I/O device to the one of said I/O expansion bus and said I/O transfer interconnection in accordance with said register for performing a transfer between said master and said I/O device.

Claim 2

Dependent Claim 130 words

In a computer system comprising a master, a memory, an I/O expansion bus, an I/O transfer interconnection not connected to the expansion bus, an I/O device connected to the I/O expansion bus and the I/O transfer interconnection, and a register configured to indicate one of said I/O expansion bus and said I/O transfer interconnection for transfers between said master and said I/O device, a transfer process comprising the steps of: (a) selecting the I/O device to the I/O expansion bus for performing a transfer on a first path between said I/O device and said memory; and (b) selecting the I/O device to the one of said I/O expansion bus and said I/O transfer interconnection in accordance with said register for performing a transfer between said master and said I/O device.

Claim 3

Dependent Claim 115 words

A process for transferring data via one of first and second data paths, said first data path including an I/O expansion bus, and said second data path bypassing said I/O expansion bus via a transfer interconnection, said process comprising the steps of: (a) storing in a register an indication whether said transfer interconnection supports transfers between said master and said I/O device; (b) if said transfer is between a memory and said I/O device, then performing said transfer via said first path; and (c) if said transfer is between a master and said I/O device, performing said transfer via said one of first and second data paths in accordance with said indication in said register.

Claim 4

Dependent Claim 115 words

A process for transferring data via one of first and second data paths, said first data path including an I/O expansion bus, and said second data path bypassing said I/O expansion bus via a transfer interconnection, said process comprising the steps of: (a) storing in a register an indication whether said transfer interconnection supports transfers between said master and said I/O device; (b) if said transfer is between a memory and said I/O device, then performing said transfer via said first path; and (c) if said transfer is between a master and said I/O device, performing said transfer via said one of first and second data paths in accordance with said indication in said register.

Claim 5

Dependent Claim 17 words

The process of claim 1, wherein transfers via said second path are initiated by only said master.

Claim 6

Dependent Claim 44 words

The process of claim 1, further comprising the step of writing, from said master to a storage location of said register, which storage location corresponds to said I/O device, an indication that said transfer interconnection supports transfers between said master and said I/O device.

Claim 7

Dependent Claim 51 words

The process of claim 1, further comprising, for each I/O device, the steps of: (a) polling said I/O device, via said first path, and (b) in response to said I/O device failing to respond in said step of polling via said first path, polling said I/O device via said second path.

Claim 8

Dependent Claim 57 words

The process of claim 5, further comprising the step of, in response to said I/O device responding to said step of polling via said second path, writing in a storage location of said register, which storage location corresponds to said I/O device, an indication that said second path supports transfers between said master and said I/O device.

Claim 9

Dependent Claim 46 words

The process of claim 1, wherein said step of transferring via said second path further comprises the step of transmitting an MIO -- SEL signal indicating a particular one of two types of registers in said I/O device to be accessed transfer via said second path.

Claim 10

Dependent Claim 35 words

The process of claim 1, further comprising the step of after said step of transferring via said second path, transmitting an MIO -- SEL signal indicating that said transfer via said second path was successful.

Claim 11

Dependent Claim 29 words

The process of claim 5, further comprising, for each I/O device, the step of: in response to said polling via said second path, transmitting said MIO -- SEL signal.

Claim 12

Dependent Claim 23 words

The process of claim 1, wherein a likelihood of processing delay in said master, by transfers via said I/O expansion bus is decreased.

Claim 13

Dependent Claim 140 words

A computer system, comprising: (a) a master, (b) a memory, (c) an I/O device, (d) a register configured to store an indication whether said transfer interconnection supports transfers between said master and said I/O device, (e) a first data path, including a first bus connected to said I/O device, for performing transfers between said memory and said I/O device and for performing transfers between said master and said I/O device if said indication is that said transfer interconnection fails to support transfers between said master and said I/O device, and (f) a second data path, including a transfer interconnection connected to said I/O device, for performing transfers between said master and said I/O device if said indication is that said transfer interconnection supports transfers between said master and said I/O device, said second data path not including the first bus.

Claim 14

Dependent Claim 140 words

A computer system, comprising: (a) a master, (b) a memory, (c) an I/O device, (d) a register configured to store an indication whether said transfer interconnection supports transfers between said master and said I/O device, (e) a first data path, including a first bus connected to said I/O device, for performing transfers between said memory and said I/O device and for performing transfers between said master and said I/O device if said indication is that said transfer interconnection fails to support transfers between said master and said I/O device, and (f) a second data path, including a transfer interconnection connected to said I/O device, for performing transfers between said master and said I/O device if said indication is that said transfer interconnection supports transfers between said master and said I/O device, said second data path not including the first bus.

Claim 15

Dependent Claim 14 words

The computer system of claim 11, wherein said transfer interconnection is a second bus.

Claim 16

Dependent Claim 59 words

The computer system of claim 12, wherein said second bus comprises: (a) a plurality of lines for transferring address and data bits of commands and responses, and (b) a register select line for transferring an indication specifying that said transfer via said plurality of lines accesses either a configuration register or an I/O space register of said I/O device.

Claim 17

Dependent Claim 67 words

The computer system of claim 11, further comprising: (a) a system bus interconnecting said master and said shared memory, and (b) an I/O bridge connected to said system bus and to both said first bus and said transfer interconnection, (c) wherein said first path further comprises said system bus and said I/O bridge and wherein said second path further comprises said system bus and said I/O bridge.

Claim 18

Dependent Claim 14 words

The computer system of claim 11, wherein said transfer interconnection is a ring connection.

Claim 19

Dependent Claim 17 words

The process of claim 2, wherein transfers via said second path are initiated by only said master.

Claim 20

Dependent Claim 38 words

The process of claim 2, wherein the step of storing said indication further comprises the step of writing said indication from said master to a storage location of said register, which storage location corresponds to said I/O device.

Claim 21

Dependent Claim 58 words

The process of claim 2, wherein said step of storing said indication further comprises, for each I/O device, the steps of: (a) polling said I/O device, via said first path, and (b) in response to said I/O device failing to respond in said step of polling via said first path, polling said I/O device via said second path.

Claim 22

Dependent Claim 51 words

The process of claim 18, wherein the step of storing said indication further comprises the step of, in response to said I/O device responding to said step of polling via said second path, writing said indication to a storage location of said register, which storage location corresponds to said I/O device.

Claim 23

Dependent Claim 46 words

The process of claim 2, wherein said step of transferring via said second path further comprises the step of transmitting an MIO -- SEL signal indicating a particular one of two types of registers in said I/O device to be accessed transfer via said second path.

Claim 24

Dependent Claim 33 words

The process of claim 2, further comprising the step of after transferring data via said second path, transmitting an MIO -- SEL signal indicating that said transfer via said second path was successful.

Claim 25

Dependent Claim 29 words

The process of claim 18, further comprising, for each I/O device, the step of: in response to said polling via said second path, transmitting said MIO -- SEL signal.

Claim 26

Dependent Claim 23 words

The process of claim 2, wherein a likelihood of processing delay in said master, by transfers via said I/O expansion bus is decreased.

Claim 27

Dependent Claim 64 words

The computer system of claim 11, wherein the computer comprises a plurality of I/O devices, at least one I/O device being a non-blocking I/O device and at least one I/O device being a conventional I/O device and wherein each non-blocking I/O device is connected to the first and second data paths and each conventional I/O device is connected only to the first data path.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-08-24	2002-02-23	2002-08-25	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-08-24	2006-02-23	2006-08-25	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-08-24	2010-02-23	2010-08-25	$7700.00	Window Closed / Lapsed

Non-blocking peripheral access architecture having a register configure to indicate a path selection for data transfer between a master, memory, and an I/O device

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