Data transfer controller incorporating direct memory access channels and address mapped input/output windows

Claim 2

A data transfer controller for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of relatively lower performance devices is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices while isolating said first set of devices from said relatively lower performing second set of devices comprising: (a) direct memory access means, coupled to said first bus and to said second bus, including at least one direct memory access channel means, for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus; (b) input/output controller means, coupled to said first bus and to said second bus, including at least one address mapped input/output port means, for providing direct access to said second set of devices by said CPU; (c) means for interconnecting said first bus to said direct memory access means and to said input/output controller means; and (d) means for interconnecting said second bus to said direct memory access means and said input/output controller means wherein said means for interconnecting said second bus to said access means and said controller means further comprises: (e) packing and funneling network means, coupled to both said access means and said controller means, for accommodating variable width data transfers between said first bus and said second bus; and (f) transfer means, including multiplexing means, coupled between said packing and funneling network means, said access means, said controller means and to said second bus, for multiplexing address and data signals being transferred to said second bus.

Claim 3

A data transfer controller as set forth in claim 1 wherein said transfer means includes a transceiver, coupled between said multiplexing means and said second bus, for transmitting and receiving signals being transferred to and from said second bus.

Claim 4

A data transfer controller as set forth in claim 2 further comprising means for prioritizing access to said port means and said channel means.

Claim 5

A data transfer controller as set forth in claim 3 further comprising means for prioritizing access to said port means whenever a plurality of port means exists.

Claim 6

A data transfer controller as set forth in claim 3 further comprising means for prioritizing access to said channel means whenever a plurality of channel means exists.

Claim 7

A data transfer controller as set forth in claim 1 further comprising means for checking parity for both data and address transfers.

Claim 8

A data transfer controller as set forth in claim 1 including a plurality of sets of internal registers wherein said plurality of sets of registers comprises: (a) a set of internal registers for controlling and maintaining a status of global operation of the data transfer controller; (b) a set of internal registers for controlling and maintaining a status of said channel means; (c) a set of internal registers for controlling and maintaining a status of said port means; and (d) a set of internal registers for buffering data transfers via said channel means.

Claim 9

A data transfer controller as set forth in claim 7 wherein said means for interconnecting said first bus to said access means and said controller means further comprises means for initializing said plurality of sets of registers.

Claim 10

A data transfer controller as set forth in claim 1 further comprising means for separating operation of said access means from program execution by said CPU.

Claim 11

A data transfer controller as set forth in claim 1 wherein said access means is programmable.

Claim 12

A data transfer controller as set forth in claim 10 wherein said access means is programmed during initialization by said CPU to determine data transfer addresses independent of the CPU during operation of the data transfer controller.

Claim 13

A data transfer controller as set forth in claim 1 wherein said access means further comprises means for performing nonsequential transfers.

Claim 14

A data transfer controller as set forth in claim 1 said access means further comprises: (a) queue means for buffering data being transferred between said first bus and said second bus; and (b) programmable internal register means for controlling the operation of said queue means.

Claim 15

A data transfer controller as set forth in claim 13 wherein each of said at least one channel means further comprises: (a) first multiplexing means for selectively transferring word length data input to said access means from said first bus and for selectively transferring packed data, input to said access means from said packing and funneling network means, into said queue means; (b) first packing/funneling register means, coupled to said first multiplexing means and said packing and funneling network means, for storing data during packing and funneling operations; and (c) second multiplexing means for selectively transferring data output from said queue means, to be funneled to said packing and funneling network means via said first register means, and for selectively transferring packed data input from said packing and funneling network to said first multiplexing means via said first register means.

Claim 16

A data transfer controller as set forth in claim 13 wherein the data buffered in said queue means may be directly manipulated by said CPU to avoid a latency associated with data transfers between said first bus and said queue means.

Claim 17

A data transfer controller as set forth in claim 1 wherein said access means further comprises transfer rate control means in a path between said first bus and said second bus.

Claim 18

A data transfer controller as set forth in claim 1 further comprising means for performing bus sizing.

Claim 19

A data transfer controller as set forth in claim 1 further comprising means for overlapping port means operation with the operation of said set of devices attached to said first bus.

Claim 20

A data transfer controller as set forth in claim 1 further comprising means for overlapping channel means operation with the operation of said set of devices attached to said first bus.

Claim 21

A data transfer controller as set forth in claim 1 further comprising means for performing data packing and unpacking.

Claim 22

A data transfer controller as set forth in claim 1 further comprising means for providing separating operation of port means within said controller means from program execution by said CPU.

Claim 23

A data transfer controller as set forth in claim 21 wherein said separate operation is accomplished via means for performing overlapped input/output via implementation of read ahead and write behind operation.

Claim 24

A data transfer controller as set forth in claim 1 further comprising means for determining if a first bus address input to said port means is within a preselected port means address space.

Claim 25

A data transfer controller as set forth in claim 23 wherein each of at least one input/output port means further comprises means for performing address translation between a first bus address input to the port means and a second bus address to be output from the port means, whenever the port means is being addressed by said first bus.

Claim 26

A data transfer controller as set forth in claim 24 wherein said address translation is performed over a power of two range of addresses of said first bus to an independent range of addresses of said second bus.

Claim 27

A data transfer controller as set forth in claim 25 wherein said means for performing said address translation further comprises means for masking out a preselected number of high order bits from the first bus address and replacing said bits with the same number of high order bits of a second bus address.

Claim 28

A data transfer controller as set forth in claim 23 wherein each of said at least one port means further comprises means for multiplexing data to and from said packing and funneling network means.

Claim 29

A data transfer controller as set forth in claim 22 wherein each of said port means further comprises a pack/funnel register for buffering data being transferred to and from said packing and funneling network means by said port means.

Claim 30

A data transfer controller as set forth in claim 28 wherein said means for performing overlapped input/output further comprises: (a) means for determining if a given port means is enabled to perform a read ahead/write behind operation instead of direct read/write operation; and (b) means for immediately responding to an access by said first bus whenever a read ahead/write behind operation is enabled even though an access by said second bus may be in progress.

Claim 31

A data transfer controller as set forth in claim 29 wherein said means for responding further comprises: (a) means for latching the address of said first bus access; (b) means for determining if said access is a read; (c) means for performing said read, independent of any access on said second bus, whenever it is determined that said access is a read.

Claim 32

A data transfer controller as set forth in claim 30 further comprising means for performing a write, independent of any access on said second bus, whenever it is determined that said access is not a read.

Claim 33

A data transfer controller as set forth in claim 31 wherein said means for performing said read further comprises: (a) means, coupled to said first bus, for immediately transferring the contents of said pack/funnel register to said first bus whenever a given port means is accessed by a first bus read; (b) means, coupled to said first bus, for buffering an untranslated input address of the first bus access; (c) means, coupled to said means for buffering untranslated addresses, for translating said input address; and (d) means, coupled to said second bus, for performing a second bus read using said translated address and for storing the data read off said second bus in said pack/funnel register.

Claim 34

A data transfer controller as set forth in claim 32 further comprising means, coupled to said pack/funnel register, for obtaining packed data from said packing and funneling network means for storage in said pack/funnel register.

Claim 35

A data transfer controller as set forth in claim 33 further comprising means for inhibiting a subsequent access to a given port means via said first bus while said port means performs a read ahead/write behind operation.

Claim 36

A data transfer controller as set forth in claim 31 wherein said means for performing said write further comprises: (a) means, coupled to said first bus, for storing data being transferred from said first bus to said second bus, via said port means, in said pack/funnel register whenever said port means is accessed by a first bus write; (b) means, coupled to said first bus, for buffering an untranslated input address of the first bus access; (c) means, coupled to said means for buffering untranslated addresses, for translating said input address; and (d) means, coupled to said second bus, for performing a second bus write using said translated address and the data stored in said pack/funnel register.

Claim 37

A data transfer controller as set forth in claim 35 further comprising means, coupled to said pack/funnel register, enabling data to be funneled from said pack/funnel register to said second bus via said packing and funneling network means.

Claim 38

A data transfer controller as set forth in claim 36 further comprising means for inhibiting a subsequent access to a given port means via said first bus while said port means performs a read ahead/write behind operation.

Claim 39

A data transfer controller as set forth in claim 22 further comprising means for performing said read ahead and write behind operations in parallel wherein a first one of said port means is utilized to perform said read ahead function while a second one of said port means is used to perform the write behind function in parallel.

Claim 40

A data transfer controller as set forth in claim 1 wherein said packing and funneling network means further comprises: (a) means for packing data on a transfer from said second bus to said first bus, including means for coverting a number of byte and half word transfers on said second bus to a smaller number of half words and word transfers on said first bus; and (b) means for buffering data being packed, by said means for packing, in order to facilitate full word transfers of packed data to said first bus.

Claim 41

A data transfer controller as set forth in claim 1 said packing and funneling network means further comprises: (a) means for funneling data on a transfer from said first bus to said second bus, including means for converting a number of word and half word transfers on said first bus to a larger number of half word and byte transfers on said second bus; and (b) means for buffering data being funneled, by said means for funneling, in order to enable said means for funneling to extract half words and bytes of buffered data one at a time for transfer to said second bus.

Claim 42

A data transfer controller as set forth in claim 1 further comprising means for providing separate latency and bandwidth of accesses on said first bus from latency and bandwidth of accesses on said second bus, with concurrency between accesses on both buses.

Claim 43

A data transfer controller as set forth in claim 1 including means for configuring said access means to support block and pattern transfers between said first and second buses.

Claim 44

A data transfer controller as set forth in claim 1 configured for transferring data between two synchronous buses.

Claim 45

A data transfer controller as set forth in claim 1 configured for transferring data between two asynchronous buses.

Claim 46

A data transfer controller as set forth in claim 1 wherein said controller operates in a test mode of operation which allows the controller outputs to be driven for diagnostic purposes.

Claim 47

A data transfer controller for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of relatively lower performance devices is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices while isolating said first set of devices from said relatively lower performing second set of devices comprising: (a) direct memory access means, coupled to said first bus and to said second bus, including at least one direct memory access channel means, for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus; (b) input/output controller means, coupled to said first bus and to said second bus, including at least one address mapped input/output port means, for providing direct access to said second set of devices by said CPU; (c) means for interconnecting said first bus to said direct memory access means and to said input/output controller means; and (d) means for interconnecting said second bus to said direct memory access means and said input/output controller means, further comprising: means for swapping locations of data packets within words being transferred via the controller.

Claim 48

A data transfer controller for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of relatively lower performance devices is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices while isolating said first set of devices from said relatively lower performing second set of devices comprising: (a) direct memory access means, coupled to said first bus and to said second bus, including at least one direct memory access channel means, for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus; (b) input/output controller means, coupled to said first bus and to said second bus, including at least one address mapped input/output port means, for providing direct access to said second set of devices by said CPU; (c) means for interconnecting said first bus to said direct memory access means and to said input/output controller means; and (d) means for interconnecting said second bus to said direct memory access means and said input/output controller means, further comprising: means for swapping locations of data packets within words being transferred via the controller.

Claim 49

A data transfer controller as set forth in claim 46 further comprising means for decoupling the latency and band-width of accesses on said first bus from the latency and bandwidth of accesses on said second bus, with concurrency between accesses on both buses.

Claim 50

A data transfer controller as set forth in claim 46 including means for configuring said access means to support block and pattern transfers between said first and second buses.

Claim 51

A data transfer controller as set forth in claim 46 configured for transferring data between two synchronous buses.

Claim 52

A data transfer controller as set forth in claim 46 configured for transferring data between two asynchronous buses.

Claim 53

A data transfer controller as set forth in claim 46 wherein said controller operates in a test mode of operation which allows the controller outputs to be driven for diagnostic purposes.

Claim 54

A data transfer controller for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit *"CPU"), is attached, and a second bus to which a second set of relatively lower performance devices is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices while isolating said first set of devices rom said relatively lower performing second set of devices comprising: (a) direct memory access means, coupled to said first bus and to said second bus, including at least one direct memory access channel means, for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus; (b) input/output controller means, coupled to said first bus and to said second bus, including at least one address mapped input/output port means, for providing direct access to said second set of devices by said CPU; (c) means for interconnecting said first bus to said direct memory access means and to said input/output controller means; and (d) means for interconnecting said second bus to said direct memory access means and said input/output controller means; and (e) a plurality of sets of internal registers wherein said plurality of sets of registers comprises: (i) a set of internal registers for controlling and maintaining a status of the global operation of the data transfer controller; (ii) a set of internal registers for controlling and maintaining a status of said channel means; (iii) a set of internal registers for controlling and maintaining a status of said port means; and (iv) a set of internal registers for buffering data transfers via said channel means; wherein said means for interconnecting said first bus to said access means and said controller mans further comprises means for initializing said plurality of sets of registers; and further comprising a plurality of signal paths used for carrying CPU and device generated signals to and from said plurality of sets of internal registers, which serve to initialize and control data transfer operations.

Claim 55

A data transfer controller for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit *"CPU"), is attached, and a second bus to which a second set of relatively lower performance devices is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices while isolating said first set of devices rom said relatively lower performing second set of devices comprising: (a) direct memory access means, coupled to said first bus and to said second bus, including at least one direct memory access channel means, for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus; (b) input/output controller means, coupled to said first bus and to said second bus, including at least one address mapped input/output port means, for providing direct access to said second set of devices by said CPU; (c) means for interconnecting said first bus to said direct memory access means and to said input/output controller means; and (d) means for interconnecting said second bus to said direct memory access means and said input/output controller means; and (e) a plurality of sets of internal registers wherein said plurality of sets of registers comprises: (i) a set of internal registers for controlling and maintaining a status of the global operation of the data transfer controller; (ii) a set of internal registers for controlling and maintaining a status of said channel means; (iii) a set of internal registers for controlling and maintaining a status of said port means; and (iv) a set of internal registers for buffering data transfers via said channel means; wherein said means for interconnecting said first bus to said access means and said controller mans further comprises means for initializing said plurality of sets of registers; and further comprising a plurality of signal paths used for carrying CPU and device generated signals to and from said plurality of sets of internal registers, which serve to initialize and control data transfer operations.

Claim 56

A data transfer controller as set forth in claim 52 wherein said plurality of signal paths comprise the pins of an integrated circuit package.

Claim 57

A data transfer controller for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of relatively lower performance devices is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices while isolating said first set of devices from said relatively lower performing second set of devices comprising: (a) direct memory access means, coupled to said first bus and to said second bus, including at least one direct memory access channel means, for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus; (b) input/output controller means, coupled to said first bus and to said second bus, including at least one address mapped input/output port means, for providing direct access to said second set of devices by said CPU; (c) means for interconnecting said first bus to said direct memory access means and to said input/output controller means; and (d) means for interconnecting said second bus to said direct memory access means and said input/output controller means wherein said controller operates in parallel with at least one data transfer controller, to which it is connected, in a master/slave relationship.

Claim 58

A data transfer controller for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of relatively lower performance devices is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices while isolating said first set of devices from said relatively lower performing second set of devices comprising: (a) direct memory access means, coupled to said first bus and to said second bus, including at least one direct memory access channel means, for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus; (b) input/output controller means, coupled to said first bus and to said second bus, including at least one address mapped input/output port means, for providing direct access to said second set of devices by said CPU; (c) means for interconnecting said first bus to said direct memory access means and to said input/output controller means; and (d) means for interconnecting said second bus to said direct memory access means and said input/output controller means wherein said controller operates in parallel with at least one data transfer controller, to which it is connected, in a master/slave relationship.

Claim 61

A method as set forth in claim 55 further comprising the step of packing data being transferred from said second bus to said first bus to accommodate variable width data transfers.

Claim 62

A method as set forth in claim 56 further comprising the step of funneling data being transferred from said first bus to said second bus to accommodate variable width data transfers.

Claim 63

A method as set forth in claim 55 further comprising the step of prioritizing access to said port means and said channel means.

Claim 64

A method as set forth in claim 58 further comprising the step of prioritizing access to said port means whenever a plurality of port means exists.

Claim 65

A method as set forth in claim 58 further comprising the step of prioritizing access to said channel means whenever a plurality of channel means exists.

Claim 66

A method as set forth in claim 55 further comprising the step of checking parity for both data and address transfers.

Claim 67

A method as set forth in claim 55 further comprising the step of initializing a plurality of sets of registers used for controlling said controller means and said channel means.

Claim 68

A method as set forth in claim 55 wherein said set of isolating when transferring via said access means further comprises the step of separating operation of said access means from program execution by said CPU.

Claim 69

A method as set forth in claim 55 wherein said step of isolating via said access means further comprises the step of programming said access means to determine data transfer addresses independent of the CPU operation.

Claim 70

A method as set forth in claim 55 wherein said step of transferring via said access means is performed non-sequentially.

Claim 71

A method as set forth in claim 55 wherein the step of isolating via said channel means further comprises the step of controlling the transfer rate between said first bus and said second bus.

Claim 72

A method as set forth in claim 55 further comprises the step of performing bus sizing.

Claim 73

A method as set forth in claim 55 wherein said step of isolating via said port means further comprises the step of overlapping port means operation with the operation of said set of devices attached to said first bus.

Claim 74

A method as set forth in claim 55 wherein said step of isolating via said channel means further comprises the step of overlapping channel means operation with the operation of said set of devices attached to said first bus.

Claim 75

A method as set forth in claim 55 wherein the step of isolating via said port means further comprises the step of separating operation of said port means within said controller means from program execution by said CPU.

Claim 76

A method as set forth in claim 55 further comprising the step of determining if a first bus address input to said port means is within a preselected port means address space.

Claim 77

A method as set forth in claim 71 further comprising the step of translating a first bus address input to a port means to a second bus address to be output from the port means, whenever the port means is being addressed by said first bus.

Claim 78

A method as set forth in claim 55 further comprising the steps of: (a) packing data on a transfer from said second bus wherein said step of packing further includes the step of converting a number of byte and half word transfers on said second bus to a smaller number of half words and word transfers on said first bus; and (b) buffering data being packed in order to facilitate full word transfers of packed data to said first bus.

Claim 79

A method as set forth in claim 55 further comprising the step of funneling data on a transfer from said first bus to said second bus wherein said step of funneling further includes the step of converting a number of word and half word transfers on said first bus to a larger number of half word and byte transfers on said second bus.

Claim 80

A method as set forth in claim 74 wherein said step of converting further comprises the steps of: (a) buffering data being funneled; and (b) extracting half words and bytes of buffered data, one at a time, for transfer to said second bus.

Claim 81

A method as set forth in claim 55 further comprising the step of providing separate latency and bandwidth of accesses on said first bus from latency and bandwidth of accesses on said second bus, with concurrency between accesses on both buses.

Claim 84

A method as set forth in claim 77 wherein the step of isolating via said channel means further comprises the step of multiplexing word length data input to said access means from said first bus with packed word length data being transferred via said access means from said second bus, for buffering in said queue means.

Claim 85

A method as set forth in claim 77 wherein the data buffered in said queue means may be directly manipulated by said CPU to avoid a latency associated with data transfers between said first bus and said queue means.

Claim 88

A method as set forth in claim 80 wherein said step of separating further comprises the step of buffering data being transferred by said port means to and from said second bus.

Claim 89

A method as set forth in claim 81 wherein said step of performing overlapped input/output further comprises the steps of: (a) determining if a given port means is enabled to perform a read ahead/write behind operation instead of direct read/write operation; and (b) responding immediately to an access by said first bus whenever a read ahead/write behind operation is enabled even though an access by said second bus may be in progress.

Claim 90

A method as set forth in claim 82 wherein said step of responding further comprises the steps of: (a) latching the address of said first bus access; (b) determining if said access is a read; and (c) performing said read, independent of any access on said second bus, whenever it is determined that said access is a read.

Claim 91

A method as set forth in claim 83 further comprising the step of performing a write, independent of any access on said second bus, whenever it is determined that said access is not a read.

Claim 92

A method as set forth in claim 84 wherein said step of performing said read further comprises the steps of: (a) transferring packed data, stored in said port means, to said first bus whenever a given port means is accessed by a first bus read; (b) buffering an untranslated input address of the first bus access; (c) translating said input address to a corresponding second bus address; (d) reading data off said second bus using said translated address; and (e) storing data read off said second bus in said port means.

Claim 93

A method as set forth in claim 85 further comprising the step of inhibiting a subsequent access to a given port via said first bus while said port performs a read ahead/write behind operation.

Claim 94

A method as set forth in claim 84 wherein said step of performing said write further comprises the steps of: (a) storing data being transferred from said first bus to said second bus, via said port means, in said port means whenever said port means is accessed by a first bus write; (b) buffering an untranslated input address of the first bus access; (c) translating said input address to a corresponding second bus address; and (d) performing a second bus write using said translated address and the data stored in said port means.

Claim 95

A method as set forth in claim 87 further comprising the step of funneling data from said port means to said second bus via a packing and funneling network means.

Claim 96

A method as set forth in claim 88 further comprising the step of inhibiting a subsequent access to a given port via said first bus while said port performs a read ahead/write behind operation.

Claim 97

A method as set forth in claim 80 further comprising the step of performing said read ahead and write behind operations in parallel where a first one of said port means is utilized to perform said read ahead function while a second one of said port means is used to perform the write behind function in parallel.