EP0204960A2
Expired / Lapsed
EP
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Multiple port integrated DMA and interrupt controller and arbitrator
Assignee: International Business Machines Corp
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Filing: 1986-05-06
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Granted: —
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Expires: 2006-05-06
Abstract
Abstract Both DMA access and character interrupt driven access modes of service are provided to multiple communication ports by an integrated arbitration DMA/interrupt controller 3 utilizing its own resident randomly accessible memory. Pipelined logic control architecture for handling service mode adaptations for each individual port and for managing memory accesses to main system memory enables the use of the random access memory with its inherent time delays in a manner that virtually eliminates the effect of any time delay in overall memory access throughput.
Inventors
- 👤 Gilbert Steven Burrus, Jr.
- 👤 Ronald Julius Cooper
- 👤 Michael Raymond Marr
- 👤 John Carmine Pescatore
- 👤 Mario Anthony Marsico
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 13:57
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/32; G06F13/34
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
207 words
A multi-port communications system data transfer service combined request arbitrator, direct memory access and interrupt driven access controller for a bus connected processor and memory system providing communications services, characterized in that it comprises : a communications port service request arbitration means connected to a plurality of communications ports and receiving therefrom a plurality of contemporaneous requests for data transfer service, said arbitration means having a means for identifying the highest priority service request from among said contemporaneous requests and means for issuing a channel identification therefor; a direct memory access control means connected to said arbitration means for receiving said channel identification and responsive thereto for issuing a direct memory access bus request; means responsive to a receipt from said processor of a bus grant signal for issuing to said processor a direct memory access address identifying the memory location for reading or writing data and for issuing a communications port service control signal; and an interrupt control means connected for receiving said channel identification from said arbitration means and responsive thereto for issuing interrupt signals to said processor; said interrupt control means being responsive to the receipt of an interrupt acknowledgement signal from said processor for issuing a memory base address for handling said interrupt.
Claim 2
Dependent Claim
207 words
A multi-port communications system data transfer service combined request arbitrator, direct memory access and interrupt driven access controller for a bus connected processor and memory system providing communications services, characterized in that it comprises : a communications port service request arbitration means connected to a plurality of communications ports and receiving therefrom a plurality of contemporaneous requests for data transfer service, said arbitration means having a means for identifying the highest priority service request from among said contemporaneous requests and means for issuing a channel identification therefor; a direct memory access control means connected to said arbitration means for receiving said channel identification and responsive thereto for issuing a direct memory access bus request; means responsive to a receipt from said processor of a bus grant signal for issuing to said processor a direct memory access address identifying the memory location for reading or writing data and for issuing a communications port service control signal; and an interrupt control means connected for receiving said channel identification from said arbitration means and responsive thereto for issuing interrupt signals to said processor; said interrupt control means being responsive to the receipt of an interrupt acknowledgement signal from said processor for issuing a memory base address for handling said interrupt.
Claim 3
Dependent Claim
97 words
Apparatus as described in Claim 1, wherein said direct memory access control means characterized in that it comprises : randomly accessible memory, a memory access control means therefor, and a direct memory access cycle control means; said memory access control means utilizing said channel identification for accessing said random access memory for retrieving therefrom a system memory address wherein the data to or from said channel is to be handled; and said direct memory access cycle control means issues said address as a direct memory access address upon receipt of said bus grant signal from said processor.
Claim 4
Dependent Claim
125 words
Apparatus as described in Claim 2, characterized in that said memory access control means further comprises a random access memory access selector means; means receiving said channel identification; means for issuing control signals to said random access memory access selector means to gate said channel identity thereto; a random access memory data input and output buffer said buffer being connected to said direct memory access control means and to said random access memory for supplying source or destination addresses from said random access memory to said direct memory access control means and; random access memory address increment and decrement logic means connected to said direct memory access control means for indicating the end of the byte count field for a direct memory access data transfer.
Claim 5
Dependent Claim
99 words
Apparatus as described in Claim 3, characterized in that said direct memory access cycle controller comprises: a direct memory access address register connected to said random access memory data buffer and to said direct memory access control means for receiving and issuing said direct memory access address; a bus master identification register connected to said arbitration means for receiving said channel identification; and a bus master identification decoder connected to said bus master identification register for decoding said identification and providing an indication of which said channel is bus master for said busses of said processor and memory system.
Claim 6
Dependent Claim
87 words
Apparatus as described in Claims 2 through 4, characterized in that random access memory comprises: a plurality of data storage cells for holding control block data information associated with each said channel, said control block data defining the mode of data transfer service to be accorded to each said channel and, the location in said system memory for said data transfer for each said channel; and, means for selectably reading or writing said cells to construct a said control block of data within said random access memory.
Claim 7
Dependent Claim
99 words
Apparatus as described in Claims 2 through 4, characterized in that it comprises : system interface logic means connected to said direct memory access control means and to said system busses of said processor and memory system for supplying direct memory access addresses and controls to said system busses; said system interface logic means also being connected to said memory access control means of said random access memory for supplying random access memory data, address and control signals thereto for reading or writing said random access memory under control of said processor and memory system via said system busses.
Claim 8
Dependent Claim
62 words
Apparatus as described in Claims 1 to 6, characterized in that interrupt control means further comprises: a character service interrupt control means connected to said arbitration means and receiving said channel identification therefrom; a direct memory access service interrupt control means connected to said direct memory access control means; said interrupt control means supplying interrupt signals to said processor and memory system.
Claim 9
Dependent Claim
104 words
Apparatus as described in Claim 7, characterized in that said direct memory access interrupt control means further comprises: gate means receiving an indication of the identity of the present bus master for gating said identity; storing means connected to said gate means receiving said identity and storing it; interrupt signalling means connected to said storing means for signalling a processor interrupt; encoding means connected to said storing means for encoding a representation of said identity for output as a portion of the base address to which said processor is directed for the start of a service routine for said identity of said bus master.
Claim 10
Dependent Claim
106 words
Apparatus as described in Claim 7, characterized in that said character interrupt control means further comprises: storage means connected to receive channel service requests; character interrupt enabling means connected to the system data bus for receiving channel interrupt mode enabling signals; comparison means connected to said storage means and to said character interrupt enabling means for providing an indication to said processor whenever a requesting channel's request compares with said channel's enabling signal in said enabling means; and encoding means connected to said comparison means for providing a partial indication of a base address in system memory where a service routine for said enabled channel resides.
Claim 11
Dependent Claim
36 words
Apparatus as described in Claims 2 through 9 characterized in that said memory access control means further comprises: means for enhancing the probability of the occurrence of multiple pending direct memory access data transfer service requests.
Claim 12
Dependent Claim
122 words
An integrated multi-port direct memory access and interrupt arbitration and control means, characterized in that it comprises: a data transfer mode selector means for defining and controlling the direct memory access or interrupt mode of data transfer handling for a given requesting port based upon previously stored- choices therefor; a direct memory access transfer processor connected to said mode selection means and responsive to the selection of the direct memory access mode of data transfer for performing a direct memory access mode data transfer at said requesting port; an interrupt driven transfer controller connected to said mode selection means and responsive to the selection of the interrupt mode of data transfer for performing an interrupt mode data transfer at said requesting port.
Claim 13
Dependent Claim
122 words
An integrated multi-port direct memory access and interrupt arbitration and control means, characterized in that it comprises: a data transfer mode selector means for defining and controlling the direct memory access or interrupt mode of data transfer handling for a given requesting port based upon previously stored- choices therefor; a direct memory access transfer processor connected to said mode selection means and responsive to the selection of the direct memory access mode of data transfer for performing a direct memory access mode data transfer at said requesting port; an interrupt driven transfer controller connected to said mode selection means and responsive to the selection of the interrupt mode of data transfer for performing an interrupt mode data transfer at said requesting port.
Claim 14
Dependent Claim
40 words
Apparatus as described in Claim 11, wherein said interrupt driven transfer controller fur- . ther comprises: an interrupt mode request arbitrator for selecting for handling the highest priority interrupt mode request that may be present among contemporaneous competing requests therefor.
Claim 15
Dependent Claim
57 words
Apparatus as described in claim 12, characterized in that said interrupt driven transfer controller further comprises: a character interrupt controller connected to said request arbitrator for presenting an interrupt to a system microprocessor and responsive to an interrupt acknowledgement therefrom for presenting base address and controls necessary for enabling said interrupt to be processed by said microprocessor.
Claim 16
Dependent Claim
43 words
Apparatus as described in Claim 11, characterized in that said direct memory access transfer controller further comprises: a direct memory access mode request arbitrator for selecting the highest priority direct memory access mode request from among any contemporaneous competing requests therefor for processing.
Claim 17
Dependent Claim
43 words
Apparatus as described in Claim 12, characterized in that said direct memory access transfer controller further comprises: a direct memory access mode request arbitrator for selecting the highest priority direct memory access mode request from among any contemporaneous competing requests therefor for processing.
Claim 18
Dependent Claim
83 words
Apparatus as described in Claims 14 and 15, characterized in that said direct memory access transfer controller further comprises: an internal cycle controller, a random access memory, a direct memory access cycle controller, a direct memory access cycle controller interrupt controller, and bus access control logic means; said internal cycle controller accessing said random access memory and fetching control information to be used with said highest priority request; said internal cycle controller initiating said direct memory access and controlling said bus access logic.
Claim 19
Dependent Claim
37 words
Apparatus as described in Claims 11 through 18, characterized in that said direct memory access request arbitration means further comprises: means for enabling said direct memory access arbitration means to accumulate multiple pending requests for DMA service.
References Cited (Backward Citations)
EP0079698A2
Cited
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