Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
108 words
A data processing system having an apparatus for controlling interruptions in the program, wherein a series of input-output units (I/ O ) is connected by means of a system bus to a central unit which is capable of accepting at least one category of vectored interrupts requested by the I/O units and a category of non-vectored interrupts generated by the operating system of the program in consequence of predetermined operations, characterised by means capable of subdividing at least one of said categories of interrupts into a plurality of priority levels, said means being conditioned by an interrupt of a predetermined level to mask interrupts of a lower-priority level.
Claim 2
Dependent Claim
108 words
A data processing system having an apparatus for controlling interruptions in the program, wherein a series of input-output units (I/ O ) is connected by means of a system bus to a central unit which is capable of accepting at least one category of vectored interrupts requested by the I/O units and a category of non-vectored interrupts generated by the operating system of the program in consequence of predetermined operations, characterised by means capable of subdividing at least one of said categories of interrupts into a plurality of priority levels, said means being conditioned by an interrupt of a predetermined level to mask interrupts of a lower-priority level.
Claim 3
Dependent Claim
69 words
A system according to claim 1, characterised in that the said means are capable of dividing vectored interrupts into at least two levels, the I/O units which are capable of requesting interrupts of a predetermined level being connected in a daisy chain, in such a manner that the relative priority of the I/O units of the same level depends on the relative position of the connection to the bus.
Claim 4
Dependent Claim
79 words
A system according to claim 2, characterised in that the said means are also capable of dividing at least one level of vectored interrupts into two sub-levels, wherein the relative priority of a sub-level decreases with the distance of the relative connection to the bus from the central unit, while the relative priority of the other sub-level increases, means being provided for connecting the two daisy chains together at the unit which from time to time requests an interrupt.
Claim 5
Dependent Claim
36 words
A system according to claim 2 or 3, characterised in that at least one I/O unit may be selectively connected to one or other end of the daisy chain by means of a corresponding command signal.
Claim 6
Independent Claim
72 words
A system according to any of the preceding claims, characterised in that interrupts- are effected by means of a corresponding routine, at least the routine of a predetermined level comprising a head, a body and a tail, means being provided for sensing the end of the body of the routine and for permitting execution of another interrupt of the same level without affecting the tail of the routine of the first interrupt.
Claim 7
Independent Claim
56 words
A system according to any of the preceding claims, wherein the non-vectored interrupts are capable of being masked by the vectored interrupts, characterised in that the said dividing means comprise a register capable of being variably loaded to identify a plurality of non-vectored interrupts, each thereof being capable of addressing a corresponding routine of the program.
Claim 8
Dependent Claim
22 words
A system according to claim 6, characterised in that the register is loaded by means of an instruction from the central unit.
Claim 9
Independent Claim
60 words
A system according to any of the preceding claims, wherein a memory is connected to the bus and wherein the I/O units are capable of establishing direct access to the memory, characterised in that the relative priority of the I/O units for the direct access is defined by the position of their connection to a corresponding line of the bus.
Claim 10
Dependent Claim
39 words
A system according to claim 8, characterised in that the unit which takes control of the bus for direct access becomes from time to time bus master of the system, while that which releases control becomes of lowest priority.
Claim 11
Dependent Claim
51 words
A system according to claim 9, charcaterised in that the control means may be selectively predisposed for releasing control of the bus at the end of each memory cycle, or at the end of a multiple exchange, or at the end of a cycle in which a higher- priority request occurs.