Patent US5799201A successfully refreshed from Google Patents.
US5799201A
Expired / Lapsed
US
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Signal processor
Assignee: US Philips Corp
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Filing: 1996-12-06
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Granted: 1998-08-25
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Expires: 2016-12-06
Abstract
Abstract A signal processor which includes a first data processing unit for processing data supplied thereto by a data bus system which operates in successive command cycles, and at least one further data processing unit operating in parallel with the first processing unit to process data supplied from the first processing unit during the command cycles. Since the further processing unit does not receive data from the bus system, that processor and still further processors can be added without requiring extension of the bus system. The parallel operation of a plurality of processing units achieves enhanced speed of computation, so that the signal processor is particularly adapted to computation of auto-correlation and cross-correlation functions and for FIR digital filtering.
Inventors
- 👤 Dietmar Lorenz
- 👤 Harald Bauer
- 👤 Rainer Dietsch
- 👤 Karl Hellwig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:24
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/06; G06F17/00; G06F17/10; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7817; G06F7/38; G06F7/48; G06F7/544; G06F7/5443; H; H04; H04B; H04B1/00; H04B1/38; H04B1/40
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
265 words
A signal processor comprising: a data bus system for supplying, during successive command cycles, data symbols to be processed; a first data processing unit having first and second data stores coupled to the bus system for storing data supplied therefrom during successive command cycles, the data symbols in said first and second stores at the end of a given command cycle being processed by said first processing unit during the next succeeding command cycle; a second data processing unit having first and second inputs respectively coupled to said first and second stores of the first processing unit for receiving therefrom during a given command cycle data symbols which had been stored therein during the immediately preceding command cycle; the second input of said second processing unit being an input of a third data store comprised therein for storing data symbols received from said second data store, the first input of said second processing unit receiving data symbols from said first data store; and the data symbols received from said first data store and the data symbols in said third data store being processed by said second processing unit concurrently with processing by the first processing unit of data symbols stored in said first and second data stores; whereby data symbols supplied by said bus system to said first processing unit during successive command cycles are made available to said first and second processing units so as to enable concurrent processing thereof by the first and second processing units and without requiring supply of data symbols from said bus system directly to said second processing unit.
Claim 2
Dependent Claim
265 words
A signal processor comprising: a data bus system for supplying, during successive command cycles, data symbols to be processed; a first data processing unit having first and second data stores coupled to the bus system for storing data supplied therefrom during successive command cycles, the data symbols in said first and second stores at the end of a given command cycle being processed by said first processing unit during the next succeeding command cycle; a second data processing unit having first and second inputs respectively coupled to said first and second stores of the first processing unit for receiving therefrom during a given command cycle data symbols which had been stored therein during the immediately preceding command cycle; the second input of said second processing unit being an input of a third data store comprised therein for storing data symbols received from said second data store, the first input of said second processing unit receiving data symbols from said first data store; and the data symbols received from said first data store and the data symbols in said third data store being processed by said second processing unit concurrently with processing by the first processing unit of data symbols stored in said first and second data stores; whereby data symbols supplied by said bus system to said first processing unit during successive command cycles are made available to said first and second processing units so as to enable concurrent processing thereof by the first and second processing units and without requiring supply of data symbols from said bus system directly to said second processing unit.
Claim 3
Dependent Claim
123 words
A signal processor as claimed in claim 1, comprising one or more further data processing units, each having a data store coupled in series to the data store of the preceding processing unit and each having an input coupled to an output of said first data store in said first processing unit; the data store of each further processing unit receiving data symbols from the data store of the preceding processing unit during each command cycle and processing the received data during the next succeeding command cycle; whereby data symbols supplied by said bus system are concurrently processed by all of said processing units and without requiring supply of data symbols from said bus system directly to any of said further processing units.
Claim 4
Dependent Claim
47 words
A signal processor as claimed in claim 1, wherein during each command cycle each of said processing units derives the product of data symbols received thereby and stored therein and forms a running summation of all products so derived during that command cycle and previous command cycles.
Claim 5
Dependent Claim
87 words
A signal processor as claimed in claim 2, wherein each of said further data processing units further comprises: a multiplier having a pair of inputs respectively coupled to a data store of that processing unit and to said first data store of said first processing unit; an arithmetic/logic unit having a first input coupled to an output of said multiplier; and an accumulator having an input coupled to an output of said arithmetic/logic unit, and having an output coupled to a second input of said arithmetic/logic unit.
Claim 6
Dependent Claim
15 words
A signal processor as claimed in claim 4, wherein said arithmetic/logic unit is an adder/subtracter.
Claim 7
Dependent Claim
28 words
A signal processor as claimed in claim 1 comprised in a radio transceiver, the data supplied by said bus system representing signals transmitted or received by said transceiver.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-24 | 2002-02-23 | 2002-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-24 | 2006-02-23 | 2006-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-24 | 2010-02-23 | 2010-08-25 | $7700.00 | Window Closed / Lapsed |