← Back to Patent Explorer
US5175702A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital signal processor architecture with plural multiply/accumulate devices

Assignee: International Business Machines Corp
•
Filing: 1991-01-22
•
Granted: 1992-12-29
•
Expires: 2011-01-22
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An improved digital signal processor (DSP) architecture includes several multiply/accumulate devices (M-Unit 0-K) connected to the DSP bus through a delay line and elements for simultaneously operating the multiply/accumulate devices and a device for selectively storing accumulated values into a pre-assigned Dual-Port Randomly Accessible Memory area.

Inventors

  • 👤 Jean-Paul Beraud
  • 👤 Claude Galand

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 01:57
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/5443

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 120 words
An improved digital signal processor (DSP) architecture for computing values (R) by accumulating products of values from a first set of values (X) sequentially fed at a given rate, with values from a second set of P values (A), said improved DSP including: K Multiply-Add Units (M-UNIT)s, K being a submultiple of P; means for feeding each X value into all M-UNITs in parallel; means for feeding said A values into said M-UNITs through a first delay line at said given rate, whereby K values R are being computed by successive accumulations; and, a program controlled logic means including second delay line means connected to said M-UNITs and controlling on-the-fly storage of computed R values into Random Access Storage means.
Claim 2
Dependent Claim 120 words
An improved digital signal processor (DSP) architecture for computing values (R) by accumulating products of values from a first set of values (X) sequentially fed at a given rate, with values from a second set of P values (A), said improved DSP including: K Multiply-Add Units (M-UNIT)s, K being a submultiple of P; means for feeding each X value into all M-UNITs in parallel; means for feeding said A values into said M-UNITs through a first delay line at said given rate, whereby K values R are being computed by successive accumulations; and, a program controlled logic means including second delay line means connected to said M-UNITs and controlling on-the-fly storage of computed R values into Random Access Storage means.
Claim 3
Dependent Claim 75 words
An improved digital signal processor according to claim 1 and wherein each M-UNIT includes: a multiplier having a first input connected to said first registers (RX) and a second input connected to said first delay line; a two input adder device; means for connecting one adder input to said multiplier; two accumulator/buffers; means for alternatively connecting said accumulator/buffers to said adder device; and, means for selectively feeding back an accumulator/buffer contents into said adder device.
Claim 4
Dependent Claim 23 words
An improved digital signal processor according to claim 2 wherein said first M-UNIT (M-UNIT 0) adder function is performed by the processor ALU.
Claim 5
Dependent Claim 59 words
An improved digital signal processor as claimed in claim 1, 2 or 3, wherein said program controlled logic means includes: a decoding device; microcode means for providing said decoding device with a synchro pulse; second delay line means connected to said decoding device and provided with taps; and, means for connecting said taps to control Dual Port RAM operations.
Claim 6
Dependent Claim 37 words
An improved digital signal processor as claimed in claim 4 and further, including a modulo index register connected to said control logic device and providing Dual Port RAM addresses for storing selected M-UNITs outputs into said RAM.

References Cited (Backward Citations)

US4490807A Cited
US4694416A Cited
JPS62274426A Cited
US4896285A Cited
EP0320352A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-12-29 1996-06-29 1996-12-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-12-29 2000-06-29 2000-12-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-12-29 2004-06-29 2004-12-29 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag