VLSI programmable digital signal processor

Claim 1

A circuit for performing different signal processing functions on digital input data, said data being in the form of binary data words, each word being presented in a bit by bit serial manner to said circuit, each of said different functions being provided by uniquely combining a series of substantially identical algebraic subfunctions performed concurrently on said input data and partially processed input data comprising: a plurality of substantially identical algebraic digital operating units for receiving and operating on said input data to generate output data or partially processed input data, each said digital operating unit being adapted to perform said identical subfunction, and signal directing means coupled intermediate said units for moving said input data and partially processed data into and through said units concurrently in a plurality of unique patterns, each unique pattern being associated with one of said different signal processing functions, said signal directing means being responsive to preselected user input to direct data through said plurality of units in one of said unique patterns such that said input data is operated on to generate the associated one of said plurality of functions; said signal directing means including a plurality of data paths, configuration register means for receiving user provided configuration control signals, and multiplexer means responsive to said configuration register means for selectively coupling said data paths to said operating units to thereby direct data through said operating units in one of said patterns as determined by said user provided configuration control signals; said multiplexer means including a plurality of multiplexer units, one of said units being associated with each of said operating units, said multiplexer units coupled to each of said data paths, each said multiplexer unit being operated to couple its associated operating unit with each of said remaining multiplexer untis via said data paths in response to said configuration control signals; said operating units further including means for multiplying a first data word by a second data word to provide an intermediate output; and means for adding said intermediate output to a third data word to provide a first operating unit output coupled to an associated multiplexer unit, each said operating unit further including first and second registers, said registers each having an input and an output, said inputs coupled to receive and temporarily store said first and second data words, said outputs coupled to said associated multiplexer unit to enable a delayed replica of said first and second data words to be selectively coupled to others of said operating units in accordance with said configuration control signals.