US5442580A
Expired / Lapsed
US
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Parallel processing circuit and a digital signal processer including same
Assignee: Atmel Corp
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Filing: 1994-05-25
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Granted: 1995-08-15
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Expires: 2014-05-25
Abstract
Abstract A parallel processing circuit and a digital signal processor employing such a parallel circuit employs a plurality of identical multiply and accumulate (MAC) processing units. Two input signals are supplied to each of the MAC processing units. In one embodiment, a delay or a shift register delays one of the input digital signal from one MAC to another MAC. A plurality of different processed signals can be generated simultaneously based upon the supplied input digital signals, greatly increasing processing capability without increasing clock speed or increasing bandwidth access to a memory.
Inventors
- 👤 Gerhard P. Fettweis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:51
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/5443
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
320 words
A parallel processing circuit for receiving a first digital signal and a second digital signal and for generating a plurality of processed signals, said circuit comprising: a plurality of substantially identical processing means each having two inputs for receiving two input digital signals and for generating a processed signal, wherein said processed signal is an arithmetic operation of said two input digital signals; means for supplying said first digital signal simultaneously to a first input of all of said plurality of processing means; means for supplying said first digital signal to a first delay means and for generating a first delayed digital signal therefrom; first multiplexer means for receiving said first delayed digital signal and said first digital signal and a first control signal for generating a first multiplexed signal in response thereto, wherein said first multiplexed signal being either said first delayed digital signal or said first digital signal in response to said first control signal; second multiplexer means for receiving said first multiplexed signal and said second digital signal and a second control signal for generating a second multiplexed signal in response thereto, wherein said second multiplexed signal being either said first multiplexed signal or said second digital signal in response to said second control signal; means for supplying said second multiplexed signal to a second input of one of said plurality of processing means; second delay means for receiving said second digital signal and for generating a second delayed digital signal in response thereto; third multiplexer means for receiving said second delayed digital signal and said second digital signal and a third control signal for generating a third multiplexed signal in response thereto, wherein said third multiplexed signal being either said second delayed digital signal or said second digital signal in response to said third control signal; and means for supplying said third multiplexed signal to a second input of another of said plurality of processing means.
Claim 2
Dependent Claim
320 words
A parallel processing circuit for receiving a first digital signal and a second digital signal and for generating a plurality of processed signals, said circuit comprising: a plurality of substantially identical processing means each having two inputs for receiving two input digital signals and for generating a processed signal, wherein said processed signal is an arithmetic operation of said two input digital signals; means for supplying said first digital signal simultaneously to a first input of all of said plurality of processing means; means for supplying said first digital signal to a first delay means and for generating a first delayed digital signal therefrom; first multiplexer means for receiving said first delayed digital signal and said first digital signal and a first control signal for generating a first multiplexed signal in response thereto, wherein said first multiplexed signal being either said first delayed digital signal or said first digital signal in response to said first control signal; second multiplexer means for receiving said first multiplexed signal and said second digital signal and a second control signal for generating a second multiplexed signal in response thereto, wherein said second multiplexed signal being either said first multiplexed signal or said second digital signal in response to said second control signal; means for supplying said second multiplexed signal to a second input of one of said plurality of processing means; second delay means for receiving said second digital signal and for generating a second delayed digital signal in response thereto; third multiplexer means for receiving said second delayed digital signal and said second digital signal and a third control signal for generating a third multiplexed signal in response thereto, wherein said third multiplexed signal being either said second delayed digital signal or said second digital signal in response to said third control signal; and means for supplying said third multiplexed signal to a second input of another of said plurality of processing means.
Claim 3
Dependent Claim
15 words
The circuit of claim 1 wherein said arithmetic operation is a multiply and accumulate operation.
Claim 4
Dependent Claim
82 words
The circuit of claim 2 wherein each of said processing means further comprising: means for multiplying said two input digital signals to generate a multiplied signal; means for adding said multiplied signal to a stored signal to generate an accumulate signal; means for storing said accumulate signal; and means for supplying said accumulate signal stored in said storing means to said adding means as said stored signal, and to supply said accumulate signal stored in said storing means as said processed signal.
Claim 5
Dependent Claim
32 words
The circuit of claim 2 wherein said first and second digital signals are supplied at each clock cycle and said plurality of processed signals are generated at each of said clock cycles.
Claim 6
Dependent Claim
20 words
The circuit of claim 4 comprising: wherein said second delay means delays said second digital signal by one clock cycle.
Claim 7
Dependent Claim
19 words
The circuit of claim 4 wherein said first delay means delays said first digital signal by one clock cycle.
Claim 8
Dependent Claim
14 words
The circuit of claim 6 wherein said first delay means comprises a shift register.
Claim 9
Dependent Claim
82 words
The circuit of claim 7 wherein each of said processing means further comprising: means for multiplying said two input digital signals to generate a multiplied signal; means for adding said multiplied signal to a stored signal to generate an accumulate signal; means for storing said accumulate signal; and means for supplying said accumulate signal stored in said storing means to said adding means as said stored signal, and to supply said accumulate signal stored in said storing means as said processed signal.
Claim 10
Dependent Claim
313 words
A digital signal processor comprising: means for fetching from a memory means, a first and a second digital signal; a plurality of substantially identical processing means each having two inputs for receiving two input digital signals and for generating a processed signal, wherein said processed signal is an arithmetic operation of said two input digital signals; means for supplying said first digital signal simultaneously to a first input of all of said plurality of processing means; means for supplying said first digital signal to a first delay means and for generating a first delayed digital signal therefrom; first multiplexer means for receiving said first delayed digital signal and said first digital signal and a first control signal for generating a first multiplexed signal in response thereto, wherein said first multiplexed signal being either said first delayed digital signal or said first digital signal in response to said first control signal; second multiplexer means for receiving said first multiplexed signal and said second digital signal and a second control signal for generating a second multiplexed signal in response thereto, wherein said second multiplexed signal being either said first multiplexed signal or said second digital signal in response to said second control signal; means for supplying said second multiplexed signal to a second input of one of said plurality of processing means; second delay means for receiving said second digital signal and for generating a second delayed digital signal in response thereto; third multiplexer means for receiving said second delayed digital signal and said second digital signal and a third control signal for generating a third multiplexed signal in response thereto, wherein said third multiplexed signal being either said second delayed digital signal or said second digital signal in response to said third control signal; and means for supplying said third multiplexed signal to a second input of another of said plurality of processing means.
Claim 11
Dependent Claim
313 words
A digital signal processor comprising: means for fetching from a memory means, a first and a second digital signal; a plurality of substantially identical processing means each having two inputs for receiving two input digital signals and for generating a processed signal, wherein said processed signal is an arithmetic operation of said two input digital signals; means for supplying said first digital signal simultaneously to a first input of all of said plurality of processing means; means for supplying said first digital signal to a first delay means and for generating a first delayed digital signal therefrom; first multiplexer means for receiving said first delayed digital signal and said first digital signal and a first control signal for generating a first multiplexed signal in response thereto, wherein said first multiplexed signal being either said first delayed digital signal or said first digital signal in response to said first control signal; second multiplexer means for receiving said first multiplexed signal and said second digital signal and a second control signal for generating a second multiplexed signal in response thereto, wherein said second multiplexed signal being either said first multiplexed signal or said second digital signal in response to said second control signal; means for supplying said second multiplexed signal to a second input of one of said plurality of processing means; second delay means for receiving said second digital signal and for generating a second delayed digital signal in response thereto; third multiplexer means for receiving said second delayed digital signal and said second digital signal and a third control signal for generating a third multiplexed signal in response thereto, wherein said third multiplexed signal being either said second delayed digital signal or said second digital signal in response to said third control signal; and means for supplying said third multiplexed signal to a second input of another of said plurality of processing means.
Claim 12
Dependent Claim
36 words
The digital signal processor of claim 9 wherein each of said processing means is a multiply and accumulate (MAC) means, for receiving said two input digital signals and for generating a multiply and accumulate signal therefrom.
Claim 13
Dependent Claim
86 words
The digital signal processor of claim 10 wherein each of said MAC means further comprising: means for multiplying said two input digital signals to generate a multiplied signal; means for adding said multiplied signal to a stored signal to generate an accumulate signal; means for storing said accumulate signal; and means for supplying said accumulate signal stored in said storing means to said adding means as said stored signal, and to supply said accumulate signal stored in said storing means as said multiply and accumulate signal.
Claim 14
Dependent Claim
35 words
The digital signal processor of claim 10 wherein said fetched first and second digital signals are supplied at each clock cycle and said plurality of processed signals are generated at each of said clock cycles.
Claim 15
Dependent Claim
21 words
The digital signal processor of claim 12 wherein said first delay means delays said first digital signal by one clock cycle.
Claim 16
Dependent Claim
21 words
The digital signal processor of claim 13 wherein said second delay means delays said second digital signal by one clock cycle.
Claim 17
Dependent Claim
16 words
The digital signal processor of claim 14 wherein said second delay means is a shift register.
Claim 18
Dependent Claim
86 words
The digital signal processor of claim 13 wherein each of said MAC means further comprising: means for multiplying said two input digital signals to generate a multiplied signal; means for adding said multiplied signal to a stored signal to generate an accumulate signal; means for storing said accumulate signal; and means for supplying said accumulate signal stored in said storing means to said adding means as said stored signal, and to supply said accumulate signal stored in said storing means as said multiply and accumulate signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-14 | 1999-02-13 | 1999-08-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-14 | 2003-02-13 | 2003-08-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-14 | 2007-02-13 | 2007-08-15 | $7700.00 | Window Closed / Lapsed |