IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle

Claim 2

A Very Long Instruction Word (VLIW) computer architecture comprising: at least three integrated circuit chips, each of said chips including an arithmetic logic unit and a local register file, said local register file having a plurality of on-chip read ports connected to the arithmetic logic unit for supplying two operands to said arithmetic logic unit, and said local register file having a plurality of write ports equal in number to a total number of all said arithmetic logic units of all said integrated circuit chips of said VLIW computer architecture, whereby said local register file is partitioned into a plurality of sections, each said section corresponding to one of said write ports; and a broadcast bus directly interconnecting each of said arithmetic logic units with a corresponding one of the write ports of each of said local register files, each said arithmetic logic unit when performing a write operation writing to a corresponding one of said sections of all of said local register files via said broadcast bus such that, on a given cycle, a plurality of said arithmetic logic units concurrently write results to all said local register files and any said arithmetic logic unit has access in a next cycle to said results obtained at every said arithmetic logic unit in said given cycle.

Claim 3

The architecture as recited in claim 1 wherein each of said chips includes a single arithmetic logic unit and a single local register file.

Claim 4

The architecture as recited in claim 1 wherein each of said chips includes a plurality of arithmetic logic units and a local register file.

Claim 5

The architecture as recited in claim 2 comprising four integrated circuit chips, each of said chips including a single arithmetic logic unit and a single local register file.

Claim 6

In a Very Long Instruction Word (VLIW) computer architecture having at least three integrated circuit chips, each of said chips including an arithmetic logic unit (ALU) and a local register file, said local register file having a plurality of on-chip read ports connected to the ALU for supplying two operands to said ALU, a method of optimizing the local register file organization to maximize communications between the ALUs comprising the steps of: providing in each said local register file a plurality of write ports equal in number to a total number of all said ALUs of all said integrated circuit chips of said VLIW computer architecture, whereby said local register file is partitioned into a plurality of sections, each said section corresponding to one of said write ports; an directly interconnecting each of said ALUs with a corresponding one of the write ports of each of said local register files by means of a broadcast bus, each said ALU when performing a write operation writing to a corresponding one of said sections of all of said local register files via said broadcast bus such that, on a given cycle, a plurality of said ALUs concurrently write results to all said local register files and any said ALU has access in a next cycle to said results obtained at every said ALU in said given cycle.

Claim 7

In a Very Long Instruction Word (VLIW) computer architecture having at least three integrated circuit chips, each of said chips including an arithmetic logic unit (ALU) and a local register file, said local register file having a plurality of on-chip read ports connected to the ALU for supplying two operands to said ALU, a method of optimizing the local register file organization to maximize communications between the ALUs comprising the steps of: providing in each said local register file a plurality of write ports equal in number to a total number of all said ALUs of all said integrated circuit chips of said VLIW computer architecture, whereby said local register file is partitioned into a plurality of sections, each said section corresponding to one of said write ports; an directly interconnecting each of said ALUs with a corresponding one of the write ports of each of said local register files by means of a broadcast bus, each said ALU when performing a write operation writing to a corresponding one of said sections of all of said local register files via said broadcast bus such that, on a given cycle, a plurality of said ALUs concurrently write results to all said local register files and any said ALU has access in a next cycle to said results obtained at every said ALU in said given cycle.