Real-time data processing system

Claim 1

A method of reflecting data among a plurality of processing nodes interconnected through a reflective data link, comprising the steps of: establishing for each node a memory having a first data port and a second data port and having a set of addresses; establishing for each node processing means connected to said first data port of the associated memory for reading data from said memory and for writing data into said memory; sensing write data from the processing means of a node to the first data port of the associated memory that is being written into preselected addresses of said associated memory, and forwarding said sensed write data directly into said data link for reflection into the memories of other processing nodes interconnected through the data link, sensing write data on said data link being written into preselected addresses of memory, and forwarding said sensed write data from said data link directly into the associated memory of a node through the second data port of the memory.

Claim 2

A method of reflecting data among a plurality of processing nodes interconnected through a reflective data link, comprising the steps of: establishing for each node a memory having a first data port and a second data port and having a set of addresses; establishing for each node processing means connected to said first data port of the associated memory for reading data from said memory and for writing data into said memory; sensing write data from the processing means of a node to the first data port of the associated memory that is being written into preselected addresses of said associated memory, and forwarding said sensed write data directly into said data link for reflection into the memories of other processing nodes interconnected through the data link, sensing write data on said data link being written into preselected addresses of memory, and forwarding said sensed write data from said data link directly into the associated memory of a node through the second data port of the memory.

Claim 9

A method of reflecting data among a plurality of processing nodes interconnected through a data link, comprising the steps of: establishing for each processing node a memory having a first data port and a second data port and having a set of addresses; establishing for each node processing means connected to said first data port of said memory for reading data from said memory and for writing data into said memory; establishing a sense logic means for each processing node connected to said processing means, said second data port of said memory and the data link for sensing write data being written into preselected addresses of memory; setting a first predetermined range of memory addresses in each of said sense logic means; sensing write transfers being written into the memories; comparing each of the sensed write transfers to determine if said sensed write transfer is being written to an address within said first predetermined range of memory addresses; receiving and queuing sensed and compared write transfers that are written to addresses within said first predetermined range of memory addresses; transmitting queued sensed write transfers from said first queuing means onto said data link independently of said processing means; sensing a write transfer on the data link; setting a second predetermined range of memory addresses in said sense logic means; comparing a sensed write transfer sensed on the data link to determine if said sensed write transfer is written to an address within said second predetermined range of memory addresses; and queuing sensed write transfers that are written to addresses within said second predetermined range of memory addresses and releasing them into the second port of the memory independently of said processing means.

Claim 10

A method of reflecting data among a plurality of processing nodes interconnected through a data link, comprising the steps of: establishing for each processing node a memory having a first data port and a second data port and having a set of addresses; establishing for each node processing means connected to said first data port of said memory for reading data from said memory and for writing data into said memory; establishing a sense logic means for each processing node connected to said processing means, said second data port of said memory and the data link for sensing write data being written into preselected addresses of memory; setting a first predetermined range of memory addresses in each of said sense logic means; sensing write transfers being written into the memories; comparing each of the sensed write transfers to determine if said sensed write transfer is being written to an address within said first predetermined range of memory addresses; receiving and queuing sensed and compared write transfers that are written to addresses within said first predetermined range of memory addresses; transmitting queued sensed write transfers from said first queuing means onto said data link independently of said processing means; sensing a write transfer on the data link; setting a second predetermined range of memory addresses in said sense logic means; comparing a sensed write transfer sensed on the data link to determine if said sensed write transfer is written to an address within said second predetermined range of memory addresses; and queuing sensed write transfers that are written to addresses within said second predetermined range of memory addresses and releasing them into the second port of the memory independently of said processing means.

Claim 11

A method of reflecting data among a plurality of processing nodes interconnected through a data link comprising the steps of: establishing for each node a memory having at least two data ports and having a set of addresses; establishing for each node processing means connected to one data port of said memory for reading data from said memory and for writing data into said memory; establishing for each node write sense logic means connected to said processing means and the other data port of said memory for sensing write data being written into preselected addresses of said memory, for forwarding said sensed write data via said data link to other processing units interconnected through the data link and for passing data on said data link to said other port of said memory; setting a first predetermined range of memory addresses in each said write sense logic means; sensing a write transfer being written to a memory; comparing a sensed write transfer to determine if said sensed write transfer is being written to an address within said first predetermined range of memory addresses of the memory; receiving and queuing sensed compared write transfers that are written to addresses within said first predetermined range of memory addresses; and transmitting queued sensed write transfers onto said data link independently of said processing means of said processing node.

Claim 12

A method of reflecting data among a plurality of processing nodes interconnected through a data link comprising the steps of: establishing for each node a memory having at least two data ports and having a set of addresses; establishing for each node processing means connected to one data port of said memory for reading data from said memory and for writing data into said memory; establishing for each node write sense logic means connected to said processing means and the other data port of said memory for sensing write data being written into preselected addresses of said memory, for forwarding said sensed write data via said data link to other processing units interconnected through the data link and for passing data on said data link to said other port of said memory; setting a first predetermined range of memory addresses in each said write sense logic means; sensing a write transfer being written to a memory; comparing a sensed write transfer to determine if said sensed write transfer is being written to an address within said first predetermined range of memory addresses of the memory; receiving and queuing sensed compared write transfers that are written to addresses within said first predetermined range of memory addresses; and transmitting queued sensed write transfers onto said data link independently of said processing means of said processing node.

Claim 14

A method of reflecting data between a first processing node and a second processing node via a reflective data link connected between said first processing node and said second processing node for transferring data therebetween comprising the steps of: (a) establishing a first processing node having a first processor and a first dual data port memory; (b) processing data and writing processed data into one port of said first dual data port memory, said processed data being in one of a local category and a shared category; (c) sensing a write from said first processor into said one port of said first dual data port memory; (d) discriminating if said sensed write is being written to a first predetermined range of memory addresses; (e) transmitting onto said reflective data link a sensed write being written to an addresses within said first predetermined range of memory addresses; (f) establishing a second processing node having a second processor and a second dual data port memory; (g) processing data and writing processed data into one port of said second dual data port memory, said processed data being in one of a local category and a shared category; (h) sensing a write from said second processor into said one port of said second dual data port memory; (i) discriminating if said sensed write is being written to a second predetermined range of memory addresses; (j) transmitting onto said reflective data link a sensed write being written to an address within said second predetermined range of memory addresses; (k) sensing a write on the reflective data link; and (l) controlling said write sensed on the reflective data link to determine the address to which is being written, and responsive thereto releasing same into the second port of at least one of said memories.

Claim 15

A method of reflecting data between a first processing node and a second processing node via a reflective data link connected between said first processing node and said second processing node for transferring data therebetween comprising the steps of: (a) establishing a first processing node having a first processor and a first dual data port memory; (b) processing data and writing processed data into one port of said first dual data port memory, said processed data being in one of a local category and a shared category; (c) sensing a write from said first processor into said one port of said first dual data port memory; (d) discriminating if said sensed write is being written to a first predetermined range of memory addresses; (e) transmitting onto said reflective data link a sensed write being written to an addresses within said first predetermined range of memory addresses; (f) establishing a second processing node having a second processor and a second dual data port memory; (g) processing data and writing processed data into one port of said second dual data port memory, said processed data being in one of a local category and a shared category; (h) sensing a write from said second processor into said one port of said second dual data port memory; (i) discriminating if said sensed write is being written to a second predetermined range of memory addresses; (j) transmitting onto said reflective data link a sensed write being written to an address within said second predetermined range of memory addresses; (k) sensing a write on the reflective data link; and (l) controlling said write sensed on the reflective data link to determine the address to which is being written, and responsive thereto releasing same into the second port of at least one of said memories.

Claim 20

A method of real-time data processing comprising the steps of: (a) establishing a plurality of processing nodes, each including: a bus for carrying information; a processor for processing information connected to the bus means and putting write transfers on the bus means; and a memory for storing information having a port connected to the bus and including means for accepting through its port a write transfer on the bus means as transferred from the processor; (b) establishing a write only reflective data link for transferring information containing writes between the plurality of processing nodes; (c) sensing a write transfer on a bus intended for its associated memory; (d) setting a first predetermined range of memory addresses; (e) comparing a sensed write transfer to determine if said sensed write transfer is being written to an address within said first predetermined range of memory addresses; (f) queuing sensed write transfers that are written to addresses within said first predetermined range of memory addresses; and (g) transmitting queued sensed write transfers onto said reflective data link independently of its said associated processor.

Claim 21

A method of real-time data processing comprising the steps of: (a) establishing a plurality of processing nodes, each including: a bus for carrying information; a processor for processing information connected to the bus means and putting write transfers on the bus means; and a memory for storing information having a port connected to the bus and including means for accepting through its port a write transfer on the bus means as transferred from the processor; (b) establishing a write only reflective data link for transferring information containing writes between the plurality of processing nodes; (c) sensing a write transfer on a bus intended for its associated memory; (d) setting a first predetermined range of memory addresses; (e) comparing a sensed write transfer to determine if said sensed write transfer is being written to an address within said first predetermined range of memory addresses; (f) queuing sensed write transfers that are written to addresses within said first predetermined range of memory addresses; and (g) transmitting queued sensed write transfers onto said reflective data link independently of its said associated processor.

Claim 29

A method comprising the steps of: (a) providing a processing node and a reflective data link, said processing node located in a processing system interconnected to other processing units through the reflective data link; (b) providing for said processing node a memory having a first data port and a second data port and having a set of addresses and a processor connected to said first data port of said memory for reading data from said memory and for writing data into said memory; (c) sensing a write from said processor into said one port of said memory; (d) determining if said sensed write is being written to a first predetermined range of memory addresses; (e) transmitting onto said reflective data link a sensed write being written to an address in said first predetermined range of memory addresses; (f) sensing a write on the reflective data link; (g) determining if said write sensed on the reflective data link is being written to a second predetermined range of memory addresses; and (h) releasing same into the second port of said memory responsive thereto.

Claim 30

A method comprising the steps of: (a) providing a processing node and a reflective data link, said processing node located in a processing system interconnected to other processing units through the reflective data link; (b) providing for said processing node a memory having a first data port and a second data port and having a set of addresses and a processor connected to said first data port of said memory for reading data from said memory and for writing data into said memory; (c) sensing a write from said processor into said one port of said memory; (d) determining if said sensed write is being written to a first predetermined range of memory addresses; (e) transmitting onto said reflective data link a sensed write being written to an address in said first predetermined range of memory addresses; (f) sensing a write on the reflective data link; (g) determining if said write sensed on the reflective data link is being written to a second predetermined range of memory addresses; and (h) releasing same into the second port of said memory responsive thereto.

Claim 31

A method including the steps of: (a) providing a data processing system including a plurality of processing nodes and a reflective data link for transferring write only data between the processing nodes; (b) providing each processing node with a memory having two data ports and a processor connected to one port of said memory; (c) sensing a write from a processor into one port of its associated memory; (d) determining if said sensed write is being written to a first predetermined range of memory addresses; (e) transmitting onto said reflective data link a sensed write being written to an address in said first predetermined range of memory addresses; (f) sensing a write on the reflective data link; (g) determining if said write sensed on the reflective data link is being written to a second predetermined range of memory addresses; and (h) releasing same into the second port of said memory responsive thereto.

Claim 32

A method including the steps of: (a) providing a data processing system including a plurality of processing nodes and a reflective data link for transferring write only data between the processing nodes; (b) providing each processing node with a memory having two data ports and a processor connected to one port of said memory; (c) sensing a write from a processor into one port of its associated memory; (d) determining if said sensed write is being written to a first predetermined range of memory addresses; (e) transmitting onto said reflective data link a sensed write being written to an address in said first predetermined range of memory addresses; (f) sensing a write on the reflective data link; (g) determining if said write sensed on the reflective data link is being written to a second predetermined range of memory addresses; and (h) releasing same into the second port of said memory responsive thereto.