Method and apparatus for sharing information between a plurality of processing units

Claim 1

A data processing system comprising; a plurality of processor units (20,22,24) one or more of which is arranged to generate a data signal, an address signal and a memory write signal; a local bus (26, 28, 30) connected to each of said processor units and for receiving said data signal, said address signal and said memory write signal therefrom; a memory (32, 34, 36) connected to each local bus for communication via said respective local bus with its respective processor unit, said memory having a first storage area (62, 66, 70) and a second storage area (60, 64, 68), said storage areas being accessible by said local bus for transmission of a datum to and/or from said processor unit; and a global bus (12) interconnecting said second storage areas of said memories; characterised in that sensing means (38, 40, 42) are coupled to each local bus for sensing said address signal, said data signal and said memory write signal on said local bus for each processor unit which is arranged to generate said signals, said sensing means being arranged to generate a control signal when said sensing means matches said address signal with a value within a stored addressing range which defines said second storage area of said memory; the global bus (12) is coupled to said sensing means and for receiving said generated data signal, said address signal and said control signal from said sensing means; there are receiving and transmitting means (38, 40, 42, 50, 52, 54) for receiving said data signal, said address signal and said control signal from said global bus and transmitting said address signal, said data signal and said control signal to a corresponding storage address in the memory of each other of said processor units; wherein the corresponding storage addresses of said data in the second storage areas of each respective memory are related to each other by means of offset values controlled by offset means (110, 154), said offset means comprising offset subtraction means (110) for subtracting a respective offset value from each said address signal prior to receipt of said address signal by said global bus from said respective memory, and offset addition means (154) for adding the respective offset value to each said address signal after receipt of said address signal by said receiving and transmitting means of each said memory from said global bus.