Parallel digital computer architecture

Claim 1

A digital data processing apparatus for executing real-time analog format functions comprising: (a) a plurality of elemental computers, each of which is a complete digital data processor having its own central processing unit, memory, input/output means, cycle clock, external interrupt capacity, and stored program; (b) a master controller with a master cycle clock and an external interrupt capacity for regulating the transfer of data between elemental computers in conformity to an ordered sequence; (c) an MC memory; (d) master bus means comprising a data bus and an address bus, both coupled to the master controller, to the MC memory, and to the input/output means of the elemental computers; (e) a real-time clock operating at a rate commensurate with the upper frequencies of a simulation but at a substantially lower frequency than said cycle clocks, an MC interrupt line coupling said real-time clock to the master controller, and two MC interrupt lines which are an integrator interrupt line and a non-integrator interrupt line, with each elemental computer coupled to said real-time clock via at least one of said two EC interrupt lines; wherein said real-time clock generates timing comprising repetitive frames with alternating EC time slots and MC time slots in each frame, the EC time slots being divided into a plurality of non-integration time slots and one integration time slot each frame, the number of EC time slots per frame being determined by the maximum number of interchanges of data required by the program for non-integrating functions between integrating functions; (f) wherein for any given simulation program some of the elemental computers are assigned non-integrating functions and are enabled via said non-integrator interrupt line during non-integration time slots, and other of the elemental computers are assigned integrating functions and are enabled via said integration interrupt line during integration time slots, each said function corresponding to the function of one computing element of an analog computer, each elemental computer making one pass of its program to perform its assigned function digitally upon receiving an interrupt signal; (g) the master controller being enabled via said MC interrupt line during MC time slots to transfer data via said master bus means among the elemental computers, so as to be means functionally equivalent to patchcord interconnections of computing elements of an analog computer; and (h) wherein said input/output means comprises registers addressable from either the master controller via said master bus means or from the respective elemental computers.

Claim 7

The apparatus as recited in claims 1, 2, 3, 4 or 5 wherein said input/output means of some of the elemental computers includes four input registers A, B, C, D, wherein registers B and D are used to store constants which remain fixed in value as long as the real-time clock is running, with the elemental computer functioning to multiply the contents of registers A and B and also of C and D to form two inputs for the principal function that elemental computer is programmed to perform, to thereby greatly reduce the number of elemental computers required.

Claim 11

The apparatus as recited in claims 1, 2 or 4 wherein the input/output means of at least some of the elemental computers includes external data transfer means independent of said master bus means.