Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay

Claim 3

The method of claim 1, wherein the threshold time is one clock cycle.

Claim 4

The method of claim 1, wherein the first operation precedes the second operation in program order and the method further comprises executing the second operation before executing the first operation.

Claim 5

The method of claim 1, wherein a scheduler that performs the steps of selecting the first operation and selecting the second operation, comprises a sequence of entries with each entry containing memory fields that store information concerning an operation associated with the entry.

Claim 6

The method of claim 4, wherein determining availability of operands for the first operation comprises: broadcasting from a first entry, associated with the first operation, a signal identifying an operand required for execution of the first operation; forwarding from a second entry, which is associated with a third operation that alters the operand and precedes the first operation in the program order, a state signal indicating an execution stage for the third operation; determining from the state signal a minimum time until execution of the third operation is complete thereby making the operand available; and comparing the minimum time to the threshold time.

Claim 7

The method of claim 5, wherein broadcasting occurs during the first clock cycle.

Claim 8

The method of claim 6, wherein the forwarding, determining, and comparing steps occur during the second clock cycle.

Claim 9

The method of claim 1, wherein the second clock cycle immediately follows the first clock cycle, and the third clock cycle immediately follows the second clock cycle.

Claim 10

The method of claim 1, further comprising executing the first operation with a second execution unit.

Claim 11

The method of claim 9, wherein the first operation precedes the second operation in program order and the method further comprises holding up the second operation if results from the first operation are required for completion of the second operation.

Claim 12

The method of claim 1, wherein determining whether availability of operands for the first operation comprises: identifying a third operation that is being executed to generate a first of the operands for the first operation; identifying a current stage of execution of the third operation; and determining from the current stage, a minimum time until the first operand is available for the first operation.

Claim 13

A computer system comprising: a memory subsystem which stores data and instructions; and a processor operably coupled to access the data and instructions stored in the memory subsystem, wherein the processor comprises: a scheduling reservoir containing information associated with operations; an execution unit that implements at least part of a pipeline for execution of operations; issue selection logic coupled to the scheduling reservoir and associated with the execution unit, wherein each clock cycle, the issue selection logic selects from the scheduling reservoir an entry associated with an operation that is first in program order of all operations that are associated with entries in the scheduling reservoirs can be executed by the execution unit and are eligible for selection during the clock cycle; operand selection logic coupled to the execution unit, wherein each clock cycle, the operand selection logic identifies sources of operands for an operation currently in a first stage of the pipeline; and logic for setting state fields of the entries in the scheduling reservoir, wherein in response an entry being selected by the issue selection logic and the pipeline not being held up, the logic changes a state field of the selected entry from a first state indicating an associated operation is eligible for selection to a second state indicating the associated operation is ineligible for selection thereby advancing the associated operation into the pipeline, and in response to determining that an operand required for an operation currently in the first stage will be unavailable for more than a threshold time, changes the state field of an entry associated with the operation currently in the first stage back to the first state thereby removing the operation from the pipeline, making the operation eligible for selection, and allowing another operation to advance to the first stage.

Claim 14

A computer system comprising: a memory subsystem which stores data and instructions; and a processor operably coupled to access the data and instructions stored in the memory subsystem, wherein the processor comprises: a scheduling reservoir containing information associated with operations; an execution unit that implements at least part of a pipeline for execution of operations; issue selection logic coupled to the scheduling reservoir and associated with the execution unit, wherein each clock cycle, the issue selection logic selects from the scheduling reservoir an entry associated with an operation that is first in program order of all operations that are associated with entries in the scheduling reservoirs can be executed by the execution unit and are eligible for selection during the clock cycle; operand selection logic coupled to the execution unit, wherein each clock cycle, the operand selection logic identifies sources of operands for an operation currently in a first stage of the pipeline; and logic for setting state fields of the entries in the scheduling reservoir, wherein in response an entry being selected by the issue selection logic and the pipeline not being held up, the logic changes a state field of the selected entry from a first state indicating an associated operation is eligible for selection to a second state indicating the associated operation is ineligible for selection thereby advancing the associated operation into the pipeline, and in response to determining that an operand required for an operation currently in the first stage will be unavailable for more than a threshold time, changes the state field of an entry associated with the operation currently in the first stage back to the first state thereby removing the operation from the pipeline, making the operation eligible for selection, and allowing another operation to advance to the first stage.

Claim 15

The computer system of claim 12, wherein the processor and the memory subsystem are components of a motherboard.

Claim 16

The computer system of claim 13, wherein the motherboard further comprises a backplane bus operably connected to the processor, and wherein the computer system further comprises one or more devices on cards connected to the motherboard via the backplane bus.

Claim 17

The computer system of claim 12, further comprising a parallel device interface operably coupled to the processor.

Claim 18

The computer system of claim 15, further comprising a printer connected to the processor via the parallel interface.

Claim 19

The computer system of claim 12, further comprising a serial device interface operably coupled to the processor.

Claim 20

The computer system of claim 17, further comprising a modem connected to the processor via the serial interface.

Claim 21

The computer system of claim 12, further comprising a graphics adapter operably coupled to the processor.

Claim 22

The computer system of claim 19, further comprising a video display connected to the processor via the graphics adapter.

Claim 23

The computer system of claim 12, further comprising a local area network adapter operably coupled to the processor.

Claim 24

The computer system of claim 21, further comprising a network of devices connected to the processor via the network adapter.

Claim 25

The computer system of claim 12, further comprising a disk controller operably coupled to the processor.

Claim 26

The computer system of claim 23, further comprising a hard disk connected to the processor via the disk controller.

Claim 27

The computer system of claim 23, further comprising a floppy disk connected to the processor via the disk controller.

Claim 28

A processor comprising: a scheduling reservoir containing information associated with operations; an execution unit that implements at least a part of a pipeline for execution of operations; issue selection logic coupled to the scheduling reservoir and associated with the execution unit, wherein each clock cycle, the issue selection logic selects from the scheduling reservoir an entry associated with an operation that is first in program order of all operations that are associated with entries in the scheduling reservoir, can be executed by the execution unit, and are eligible for selection during the clock cycle; operand selection logic coupled to the execution unit, wherein each clock cycle, the operand selection logic identifies sources of operands for an operation currently in a first stage of the pipeline; and logic for setting state fields of the entries in the scheduling reservoir, wherein in response an entry being selected by the issue selection logic and the pipeline not being held up, the logic changes a state field of the selected entry from a first state indicating an associated operation is eligible for selection to a second state indicating the associated operation is ineligible for selection thereby advancing the associated operation into the pipeline of the execution unit, and in response to determining that an operand required for an operation currently in the first stage will be unavailable for more than a threshold time, changes the state field of an entry associated with the operation currently in the first stage back to the first state thereby removing the operation from the pipeline, making the operation eligible for selection, and allowing another operation to advance to the first stage.

Claim 29

A processor comprising: a scheduling reservoir containing information associated with operations; an execution unit that implements at least a part of a pipeline for execution of operations; issue selection logic coupled to the scheduling reservoir and associated with the execution unit, wherein each clock cycle, the issue selection logic selects from the scheduling reservoir an entry associated with an operation that is first in program order of all operations that are associated with entries in the scheduling reservoir, can be executed by the execution unit, and are eligible for selection during the clock cycle; operand selection logic coupled to the execution unit, wherein each clock cycle, the operand selection logic identifies sources of operands for an operation currently in a first stage of the pipeline; and logic for setting state fields of the entries in the scheduling reservoir, wherein in response an entry being selected by the issue selection logic and the pipeline not being held up, the logic changes a state field of the selected entry from a first state indicating an associated operation is eligible for selection to a second state indicating the associated operation is ineligible for selection thereby advancing the associated operation into the pipeline of the execution unit, and in response to determining that an operand required for an operation currently in the first stage will be unavailable for more than a threshold time, changes the state field of an entry associated with the operation currently in the first stage back to the first state thereby removing the operation from the pipeline, making the operation eligible for selection, and allowing another operation to advance to the first stage.

Claim 30

The processor of claim 26, wherein changing the value in the state field of the selected entry from the first state to the second state advances the operation associated with the selected entry to the first stage of the pipeline.