Data processing apparatus

Claim 1

A data processing apparatus which includes buffer storing means having a scalar cache memory which can be accessed by only a scalar instruction, comprising: instruction issuing means for issuing instructions in accordance with an instruction issuing order designated by a program, tentatively issuing a vector store instruction having no definitive data as an instruction not subjected to actual vector store processing, and after data is determined, finally issuing the vector store instruction as an instruction to be subjected to the actual vector store processing by interrupting the instruction issuing order; interval holding means for obtaining and holding a store interval block address to be operated by the vector store instruction tentatively issued from said instruction issuing means; passing control means for comparing a block address indicated by a scalar load/store instruction issued from said instruction issuing means with the store interval block address held by said interval holding means, if the block address falls outside the range of the store interval block addresses, enabling processing for the scalar load/store instruction, and if the block address falls within the range of the store interval block addresses, causing the processing for the scalar load/store instruction to wait until the vector store instruction is finally issued from said instruction issuing means and processed; and nullification processing means for nullifying, when a vector store instruction is tentatively issued from said instruction issuing means, block data present in said store cache memory and corresponding to a store address of the vector store instruction.