Microcomputer for resolving problems found in a program stored in a ROM

Claim 2

A microcomputer comprising: a queue buffer for prefetching each instruction of a program stored in a first ROM prior to execution of the instruction by a CPU, contents of said queue buffer being cleared by a branch-generation signal for indicating completion of execution of a branch instruction by said CPU; a second ROM for storing an instruction for branching to an address space outside an address space of said first ROM; and an address-information storing unit for storing address information, said microcomputer further comprising a ROM-output switching unit for comparing address information stored in said address-information storing unit with contents of a program counter of said queue buffer, for enabling an operation to output data from said second ROM and disabling an operation to output data from said first ROM when said address information matches said contents, and for enabling an operation to output data from said first ROM and disabling an operation to output data from said second ROM when said branch-generation signal or an instruction-code-end signal indicating that an instruction has been output from said second ROM is input.

Claim 3

A microcomputer according to claim 1 wherein said ROM-output switching circuit comprises a comparison circuit for comparing address information stored in said address-information storing unit with address data on an address bus, and a latch circuit which is put in a set state by a match signal from said comparison circuit and put in a reset state by said branch-generation signal or said instruction-code-end signal.

Claim 4

A microcomputer comprising: a queue buffer for prefetching each instruction of a program stored in a first ROM prior to execution of the instruction by a CPU, contents of said queue buffer being cleared by a branch-generation signal for indicating completion of execution of a branch instruction by said CPU: a second ROM for storing an instruction for branching to an address space outside an address space of said first ROM; and an address-information storing unit for storing address information, said microcomputer further comprising a ROM-output switching unit for comparing address information stored in said address-information storing unit with contents of a program counter of said queue buffer, for enabling an operation to output data from said second ROM and disabling an operation to output data from said first ROM when said address information matches said contents, and for enabling an operation to output data from said first ROM and disabling an operation to output data from said second ROM when said branch-generation signal or an instruction-code-end signal indicating that an instruction has been output from said second ROM is input; wherein said ROM-output switching circuit comprises a comparison circuit for comparing address information stored in said address-information storing unit with address data on an address bus, and a latch circuit which is put in a set state by a match signal from said comparison circuit and put in a reset state by said branch-generation signal or said instruction-code-end signal, wherein said ROM-output switching circuit further comprises: a first logic circuit for passing on a ROM-read signal from said queue buffer when said latch circuit is put in a reset state; a second logic circuit for receiving data output from said first ROM and passing on or blocking said first ROM output data in accordance with a signal output by said first logic circuit; a third logic circuit for passing on said ROM-read signal from said queue buffer when said latch circuit is put in a set state; and a fourth logic circuit for receiving data output by said second ROM and passing on or blocking said second ROM output data in accordance with a signal output by said third logic circuit.

Claim 5

A microcomputer comprising: a queue buffer for prefetching each instruction of a program stored in a first ROM prior to execution of the instruction by a CPU, contents of said queue buffer being cleared by a branch-generation signal for indicating completion of execution of a branch instruction by said CPU: a second ROM for storing an instruction for branching to an address space outside an address space of said first ROM; and an address-information storing unit for storing address information, said microcomputer further comprising a ROM-output switching unit for comparing address information stored in said address-information storing unit with contents of a program counter of said queue buffer, for enabling an operation to output data from said second ROM and disabling an operation to output data from said first ROM when said address information matches said contents, and for enabling an operation to output data from said first ROM and disabling an operation to output data from said second ROM when said branch-generation signal or an instruction-code-end signal indicating that an instruction has been output from said second ROM is input; wherein said ROM-output switching circuit comprises a comparison circuit for comparing address information stored in said address-information storing unit with address data on an address bus, and a latch circuit which is put in a set state by a match signal from said comparison circuit and put in a reset state by said branch-generation signal or said instruction-code-end signal, wherein said ROM-output switching circuit further comprises: a first logic circuit for passing on a ROM-read signal from said queue buffer when said latch circuit is put in a reset state; a second logic circuit for receiving data output from said first ROM and passing on or blocking said first ROM output data in accordance with a signal output by said first logic circuit; a third logic circuit for passing on said ROM-read signal from said queue buffer when said latch circuit is put in a set state; and a fourth logic circuit for receiving data output by said second ROM and passing on or blocking said second ROM output data in accordance with a signal output by said third logic circuit.

Claim 6

A microcomputer comprising: a queue buffer for prefetching each instruction of a program stored in a first ROM prior to execution of the instruction by a CPU, contents of said queue buffer being cleared by a branch-generation signal for indicating completion of execution of a branch instruction by said CPU; a second ROM for storing an instruction for branching to an address space outside an address space of said first ROM; an address-information storing unit for storing address information; and a comparison circuit for comparing address information stored in said address-information storing unit with contents of a program counter in said CPU, said microcomputer further comprising: a latch circuit which is put in a set state by a match signal from said comparison circuit, said match signal indicating that address information stored in said address-information storing unit matches contents of said program counter in said CPU, and put in a reset state by an instruction-code-end signal indicating that said second ROM has output an instruction; and a switch circuit for disabling an operation to provide an instruction from said queue buffer to said CPU and enabling an operation to provide an instruction from said second ROM to said CPU when said latch circuit is put in a set state.

Claim 7

A microcomputer comprising: a queue buffer for prefetching each instruction of a program stored in a first ROM prior to execution of the instruction by a CPU, contents of said queue buffer being cleared by a branch-generation signal for indicating completion of execution of a branch instruction by said CPU; a second ROM for storing an instruction for branching to an address space outside an address space of said first ROM; an address-information storing unit for storing address information; and a comparison circuit for comparing address information stored in said address-information storing unit with contents of a program counter in said CPU, said microcomputer further comprising: a latch circuit which is put in a set state by a match signal from said comparison circuit, said match signal indicating that address information stored in said address-information storing unit matches contents of said program counter in said CPU, and put in a reset state by an instruction-code-end signal indicating that said second ROM has output an instruction; and a switch circuit for disabling an operation to provide an instruction from said queue buffer to said CPU and enabling an operation to provide an instruction from said second ROM to said CPU when said latch circuit is put in a set state.