Semiconductor device having multiple control gates

Claim 2

A semiconductor device comprising: a semiconductor substrate; source and drain regions defined in said semiconductor substrate, with a channel region therebetween; a first insulating layer located over said semiconductor substrate including over said channel region; a floating gate locating over said first insulating layer; a second insulating layer located over said floating gate; a first control gate located over said second insulating layer; and a second control gate located over said first control gate, wherein said first and second control gates constitute a Schottky junction and allow the injection of hot carriers onto said floating gate from said first control gate when predetermined first and second voltages are applied to said first and second control gates, respectively.

Claim 5

The method according to claim 2, wherein said step of injecting includes the step of injecting hot electrons as said hot carriers onto said floating gate from said first control gate when said predetermined first reset voltage is higher than said predetermined second reset voltage, and wherein said step of resetting includes the step of resetting said predetermined first threshold voltage to said second threshold voltage, which is higher than said predetermined first threshold voltage.

Claim 8

The method according to claim 4 further comprising the steps of: applying a predetermined first read voltage to said first control gate; applying a predetermined second read voltage being equal or different to or from said first read voltage to said second control gate; flowing a current between said source and said drain; and reading data stored in said memory cell by outputting said current therefrom.

Claim 11

The method according to claim 6 further comprising the steps of: applying a predetermined first read voltage to at least one pair of said plurality pair of first and second row address lines; applying a predetermined second read voltage to said plurality of well select lines; applying a predetermined third read voltage to at least one of said plurality of column address lines; flowing a current between said first and second impurity regions; and reading data stored in at least one of said memory cells by outputting said current therefrom.

Claim 12

An electrically programmable semiconductor memory device comprising: a memory cell array having a plurality pair of first and second row address lines, a plurality of column address lines, a plurality of well select lines corresponding to said plurality of column address lines, a plurality of common wells coupled to said plurality of well select lines and a plurality of memory cells which are selectable by said plurality pair of first and second row address lines and said plurality of column address lines, each of said memory cells comprising a first and second control gates coupled to an associated one pair of said plurality pair of first and second row address lines, a floating gate, a first impurity region coupled to an associated one of said plurality of column address lines, a second impurity region, said first and second impurity regions being defined in an associated one of said plurality of common wells, said floating gate being capacitively coupled to said first control gate, wherein said first and second control gates constitute a Schottky junction; and writing means for applying a predetermined first and a predetermined second write voltages to at least one pair of said plurality pair of first and second row address lines respectively and for applying a predetermined third write voltage to at least one of said plurality of well select lines to cause first hot carriers having a first conductivity to be injected onto said floating gate from said first control gate, thereby storing data in at least one of said memory cells.

Claim 13

An electrically programmable semiconductor memory device comprising: a memory cell array having a plurality pair of first and second row address lines, a plurality of column address lines, a plurality of well select lines corresponding to said plurality of column address lines, a plurality of common wells coupled to said plurality of well select lines and a plurality of memory cells which are selectable by said plurality pair of first and second row address lines and said plurality of column address lines, each of said memory cells comprising a first and second control gates coupled to an associated one pair of said plurality pair of first and second row address lines, a floating gate, a first impurity region coupled to an associated one of said plurality of column address lines, a second impurity region, said first and second impurity regions being defined in an associated one of said plurality of common wells, said floating gate being capacitively coupled to said first control gate, wherein said first and second control gates constitute a Schottky junction; and writing means for applying a predetermined first and a predetermined second write voltages to at least one pair of said plurality pair of first and second row address lines respectively and for applying a predetermined third write voltage to at least one of said plurality of well select lines to cause first hot carriers having a first conductivity to be injected onto said floating gate from said first control gate, thereby storing data in at least one of said memory cells.

Claim 14

The memory device according to claim 8 further comprising: reading means for applying a predetermined first read voltage to at least one pair of said plurality pair of first and second row address lines for applying a predetermined second read voltage to said plurality of well select lines and for applying a predetermined third read voltage to at least one of said plurality of column address lines to flow a current between said first and second impurity regions, thereby reading data stored in at least one of said memory cells by outputting said current therefrom.