Motor system with interrupted PWM oscillation

Claim 3

The method of claim 1 wherein said zero-crossing detector further comprises a comparator coupled to said momentarily floating winding.

Claim 4

The method of claim 1 wherein said temporarily causing said pulse-width modulated signal to remain in one of said two states further comprises latching said one state of said pulse-modulated signal.

Claim 5

The method of claim 1 wherein said temporarily causing said pulse-width modulated signal to remain in one of said two states further comprises forcing said pulse-width modulated signal to a predetermined state.

Claim 6

The method of claim 1 wherein said zero-crossing detector is enabled only during said brief interval.

Claim 7

A motor control circuit for use in controlling a brushless sensorless motor in a pulse width-modulated mode of operation, said motor control circuit comprising: zero-crossing detection logic configured to detect transitions in the polarity of a voltage induced on a floating coil of a motor; control logic configured to predict an expected transition time of said transitions in polarity, and generate an interrupt output signal during a brief interval beginning shortly before said expected transition time and ending shortly after said expected transition is detected by said zero-crossing logic; and an oscillator coupled to said control logic and configured to produce a pulse-width modulated signal that transitions between two states when said interrupt output signal is not generated and remains in one of said two states when said interrupt output signal is generated by said control, and wherein the pulse-width modulated signal is for controlling an output of a drive current to the brushless sensorless motor, wherein the interrupt output signal is arranged to maintain the drive current during the brief interval beginning shortly before said expected transition time and ending shortly after said expected transition is detected by said zero-crossing logic.

Claim 8

A motor control circuit for use in controlling a brushless sensorless motor in a pulse width-modulated mode of operation, said motor control circuit comprising: zero-crossing detection logic configured to detect transitions in the polarity of a voltage induced on a floating coil of a motor; control logic configured to predict an expected transition time of said transitions in polarity, and generate an interrupt output signal during a brief interval beginning shortly before said expected transition time and ending shortly after said expected transition is detected by said zero-crossing logic; and an oscillator coupled to said control logic and configured to produce a pulse-width modulated signal that transitions between two states when said interrupt output signal is not generated and remains in one of said two states when said interrupt output signal is generated by said control, and wherein the pulse-width modulated signal is for controlling an output of a drive current to the brushless sensorless motor, wherein the interrupt output signal is arranged to maintain the drive current during the brief interval beginning shortly before said expected transition time and ending shortly after said expected transition is detected by said zero-crossing logic.

Claim 9

A motor system, comprising: a brushless sensorless motor, having a plurality of windings; and a motor control circuit as recited in claim 6, wherein the drive current controlled by said motor control circuit is supplied to said windings.

Claim 10

The motor control circuit of claim 6 further comprising: a power device configured for receiving said drive current; and a current-sensor for sensing a power device current in the power device and causing the pulse-width modulated signal to transition based on the power device current being above or below a predetermined value, the current-sensor being disabled when the interrupt output signal is generated.

Claim 11

The circuit of claim 6, wherein said zero-crossing detection logic further comprises a comparator configured to receive said voltage signal and output a logic signal based thereon.

Claim 12

The circuit of claim 2, wherein said oscillator further comprises one or more blocking elements coupled to said control logic and responsive thereto to cause said pulse-width modulated signal to temporarily remain in said one of two states when said interrupt output signal is generated by said control logic.

Claim 13

The circuit of claim 10, wherein said blocking elements include at least one selected from the group of a logical AND gate and a RS flip-flop.

Claim 14

The circuit of claim 10, wherein said blocking elements are configured to latch said one of said two states of said pulse-width modulated signal.

Claim 15

The circuit of claim 10, wherein said blocking elements are configured to force said pulse-width modulated signal to a predetermined state.

Claim 16

The circuit of claim 6, wherein said zero-crossing detection logic is enabled only during said brief interval.

Claim 17

The system of claim 7, wherein said zero-crossing detection logic further comprises a comparator configured to receive said voltage signal and output a logic signal based thereon.

Claim 18

The circuit of claim 7, wherein said oscillator further comprises one or more blocking elements coupled to said control logic and responsive thereto to cause said pulse-width modulated signal to temporarily remain in said one of two states when said interrupt output signal is generated by said control logic.

Claim 19

The circuit of claim 16, wherein said blocking elements include at least one selected from the group of a logical AND gate and a RS flip-flop.

Claim 20

The circuit of claim 16, wherein said blocking elements are configured to latch said one of said two states of said pulse-width modulated signal.

Claim 21

The circuit of claim 16, wherein said blocking elements are configured to force said pulse-width modulated signal to a predetermined state.

Claim 22

The circuit of claim 7, wherein said zero-crossing detection logic is enabled only during said brief interval.