US5319289A
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US
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Adaptive commutation delay for multi-pole brushless DC motors
Assignee: Silicon Systems Inc
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Filing: 1992-02-24
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Granted: 1994-06-07
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Expires: 2012-02-24
Abstract
Abstract A circuit to provide adaptive commutation delay for multi-pole brushless DC motors. The circuit adjusts the commutation delay as a function of the rotational speed of the motor to maximize motor torque and minimize power consumption. Unlike the prior art, the circuit avoids the need for complex circuitry or external components. The circuit may be implemented entirely within a single integrated circuit. The circuit includes a back-EMF sensing input, an oscillator, a voltage holding and proportioning circuit, one or more comparators and, optionally, an external control circuit. The back-EMF sensing input controls the operation of the oscillator. The voltage holding and proportioning circuit processes the oscillator output and provides outputs which are compared by the comparators. The comparators produce commutation delay signals and, optionally, other signals. The circuit also allows adjustment to compensate for non-ideal back-EMF-to-rotor-position correspondence or fixed time delays inherent in the commutation process.
Inventors
- 👤 Charles C. Austin
- 👤 Bertram J. White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:09
CPC Classifications
H; H02; H02P; H02P6/00; H02P6/14; H02P6/15
Claims Analysis
Total Claims: 61
Claim 1
Independent Claim
79 words
A circuit for providing commutation delay comprising: oscillating means for receiving an input and for providing a first output, wherein said first output varies substantially linearly over time for a portion of a cycle, said oscillating means comprises a sawtooth oscillator; voltage holding and attenuating means coupled to said first output, said voltage holding and attenuating means for providing a second output; comparing means coupled to said first output and to said second output for providing a third output.
Claim 2
Dependent Claim
79 words
A circuit for providing commutation delay comprising: oscillating means for receiving an input and for providing a first output, wherein said first output varies substantially linearly over time for a portion of a cycle, said oscillating means comprises a sawtooth oscillator; voltage holding and attenuating means coupled to said first output, said voltage holding and attenuating means for providing a second output; comparing means coupled to said first output and to said second output for providing a third output.
Claim 3
Dependent Claim
30 words
The circuit of claim 1 wherein said input comprises a plurality of back-EMF pulses, said first output increasing linearly over time between two adjacent of said plurality of back-EMF pulses.
Claim 4
Dependent Claim
16 words
The circuit of claim 1 wherein said sawtooth oscillator comprises a current source and a capacitor.
Claim 5
Dependent Claim
15 words
The circuit of claim 3 wherein said current source comprises a switched capacitor current source.
Claim 6
Dependent Claim
26 words
The circuit of claim 1 wherein said oscillator comprises a current source, an operational amplifier, and a capacitor in a feedback loop of said operational amplifier.
Claim 7
Dependent Claim
32 words
The circuit of claim 1 wherein said oscillating means further comprises a power consumption reduction means, said power consumption reduction means for reducing the magnitude of the current into said oscillating means.
Claim 8
Dependent Claim
14 words
The circuit of claim 6 wherein said power consumption reduction means comprises a switch.
Claim 9
Dependent Claim
41 words
The circuit of claim 1 wherein said voltage holding and attenuating means comprises a voltage holding means coupled to said first output, said voltage holding means for providing a fourth output, and a voltage attenuating means coupled to said fourth output.
Claim 10
Dependent Claim
30 words
The circuit of claim 8 wherein said voltage holding means holds a peak output value of said first output for each of a plurality of cycles of said oscillating means.
Claim 11
Dependent Claim
35 words
The circuit of claim 8 wherein said second output is of a first voltage and said fourth output is of a second voltage, said first voltage being approximately equal to one-half of said second voltage.
Claim 12
Dependent Claim
22 words
The circuit of claim 8 wherein said third output is coupled to said voltage holding means for controlling said voltage holding means.
Claim 13
Dependent Claim
59 words
The circuit of claim 8 wherein said voltage holding means comprises: a switch having a first terminal and a second terminal, said first terminal coupled to said first output and said second terminal coupled to a node; a capacitor having a first terminal coupled to said node; and an operational amplifier having a first terminal coupled to said node.
Claim 14
Dependent Claim
15 words
The circuit of claim 8 wherein said voltage attenuating means comprises a plurality of resistors.
Claim 15
Dependent Claim
14 words
The circuit of claim 8 wherein said voltage holding means comprises a track-and-hold circuit.
Claim 16
Dependent Claim
14 words
The circuit of claim 8 wherein said voltage holding means comprises a sample-and-hold circuit.
Claim 17
Dependent Claim
17 words
The circuit of claim 8 wherein said comparing means further comprises means for providing a fifth output.
Claim 18
Dependent Claim
22 words
The circuit of claim 16 wherein said fifth output is coupled to said voltage holding means for controlling said voltage holding means.
Claim 19
Dependent Claim
26 words
The circuit of claim 1 wherein said third output is coupled to said voltage holding and attenuating means for controlling said voltage holding and attenuating means.
Claim 20
Dependent Claim
17 words
The circuit of claim 1 wherein said comparing means further comprises means for providing a fifth output.
Claim 21
Dependent Claim
26 words
The circuit of claim 19 wherein said fifth output is coupled to said voltage holding and attenuating means for controlling said voltage holding and attenuating means.
Claim 22
Dependent Claim
21 words
The circuit of claim 1 wherein said comparing means provides an inhibit signal for inhibiting spurious signals present at said input.
Claim 23
Dependent Claim
26 words
The circuit of claim 1 wherein said oscillating means, said voltage holding and attenuating means, and said comparing means are incorporated into a single integrated circuit.
Claim 24
Dependent Claim
20 words
The circuit of claim 1 wherein a timing component for controlling said oscillating means is implemented as a discrete component.
Claim 25
Dependent Claim
41 words
The circuit of claim 1 wherein said voltage holding and attenuating means comprises a voltage attenuating means coupled to said first output, said voltage attenuating means for providing a fourth output, and a voltage holding means coupled to said fourth output.
Claim 26
Dependent Claim
35 words
The circuit of claim 24 wherein said fourth output is of a first voltage and said first output is of a second voltage, said first voltage being approximately equal to one-half of said second voltage.
Claim 27
Dependent Claim
30 words
The circuit of claim 24 wherein said voltage holding means holds a peak output value of said fourth output for each of a plurality of cycles of said oscillating means.
Claim 28
Dependent Claim
22 words
The circuit of claim 24 wherein said third output is coupled to said voltage holding means for controlling said voltage holding means.
Claim 29
Dependent Claim
59 words
The circuit of claim 24 wherein said voltage holding means comprises: a switch having a first terminal and a second terminal, said first terminal coupled to said first output and said second terminal coupled to a node; a capacitor having a first terminal coupled to said node; and an operational amplifier having a first terminal coupled to said node.
Claim 30
Dependent Claim
15 words
The circuit of claim 24 wherein said voltage attenuating means comprises a plurality of resistors.
Claim 31
Dependent Claim
14 words
The circuit of claim 24 wherein said voltage holding means comprises a track-and-hold circuit.
Claim 32
Dependent Claim
14 words
The circuit of claim 24 wherein said voltage holding means comprises a sample-and-hold circuit.
Claim 33
Dependent Claim
17 words
The circuit of claim 24 wherein said comparing means further comprises means for providing a fifth output.
Claim 34
Dependent Claim
22 words
The circuit of claim 32 wherein said fifth output is coupled to said voltage holding means for controlling said voltage holding means.
Claim 35
Dependent Claim
90 words
A circuit for providing commutation delay comprising: oscillating means for receiving an input and for providing a first output, wherein said first output varies substantially linearly over time for a portion of a cycle, said oscillating means comprises a sawtooth oscillator; voltage holding means coupled to said first output, said voltage holding means for providing a second output; amplifying means coupled to said first output, said amplifying means for providing a third output; comparing means coupled to said second and third outputs, said comparing means for providing a fourth output.
Claim 36
Dependent Claim
90 words
A circuit for providing commutation delay comprising: oscillating means for receiving an input and for providing a first output, wherein said first output varies substantially linearly over time for a portion of a cycle, said oscillating means comprises a sawtooth oscillator; voltage holding means coupled to said first output, said voltage holding means for providing a second output; amplifying means coupled to said first output, said amplifying means for providing a third output; comparing means coupled to said second and third outputs, said comparing means for providing a fourth output.
Claim 37
Dependent Claim
30 words
The circuit of claim 34 wherein said input comprises a plurality of back-EMF pulses, said first output increasing linearly over time between two adjacent of said plurality of back-EMF pulses.
Claim 38
Dependent Claim
16 words
The circuit of claim 34 wherein said sawtooth oscillator comprises a current source and a capacitor.
Claim 39
Dependent Claim
15 words
The circuit of claim 36 wherein said current source comprises a switched capacitor current source.
Claim 40
Dependent Claim
27 words
The circuit of claim 34 wherein said sawtooth oscillator comprises a current source, an operational amplifier, and a capacitor in a feedback loop of said operational amplifier.
Claim 41
Dependent Claim
32 words
The circuit of claim 34 wherein said oscillating means further comprises a power consumption reduction means, said power consumption reduction means for reducing the magnitude of the current into said oscillating means.
Claim 42
Dependent Claim
14 words
The circuit of claim 39 wherein said power consumption reduction means comprises a switch.
Claim 43
Dependent Claim
30 words
The circuit of claim 34 wherein said voltage holding means holds a peak output value of said first output for each of a plurality of cycles of said oscillating means.
Claim 44
Dependent Claim
34 words
The circuit of claim 34 wherein said third output is of a first voltage and said first output is of a second voltage, said first voltage being approximately equal to twice said second voltage.
Claim 45
Dependent Claim
22 words
The circuit of claim 34 wherein said fourth output is coupled to said voltage holding means for controlling said voltage holding means.
Claim 46
Dependent Claim
21 words
The circuit of claim 34 wherein said comparing means provides an inhibit signal for inhibiting spurious signals present at said input.
Claim 47
Dependent Claim
27 words
The circuit of claim 34 wherein said oscillating means, said voltage holding means, said amplifying means and said comparing means are incorporated into a single integrated circuit.
Claim 48
Dependent Claim
20 words
The circuit of claim 34 wherein a timing component for controlling said oscillating means is implemented as a discrete component.
Claim 49
Dependent Claim
59 words
The circuit of claim 34 wherein said voltage holding means comprises: a switch having a first terminal and a second terminal, said first terminal coupled to said first output and said second terminal coupled to a node; a capacitor having a first terminal coupled to said node; and an operational amplifier having a first terminal coupled to said node.
Claim 50
Dependent Claim
16 words
The circuit of claim 34 wherein said amplifying means comprises an operational amplifier and two resistors.
Claim 51
Dependent Claim
14 words
The circuit of claim 34 wherein said voltage holding means comprises a track-and-hold circuit.
Claim 52
Dependent Claim
14 words
The circuit of claim 34 wherein said voltage holding means comprises a sample-and-hold circuit.
Claim 53
Independent Claim
70 words
A method for providing commutation delay comprising the steps of: detecting a back-EMF pulse; producing a voltage proportional to the time elapsed since the back-EMF pulse occurred; holding a peak value of said voltage; proportionally reducing said peak value of said voltage to produce a proportionally reduced peak value of said voltage; comparing said voltage to said proportionally reduced peak value of said voltage; and producing a delayed commutation signal.
Claim 54
Independent Claim
70 words
A method for providing commutation delay comprising the steps of: detecting a back-EMF pulse; producing a voltage proportional to the time elapsed since the back-EMF pulse occurred; holding a peak value of said voltage; proportionally reducing said peak value of said voltage to produce a proportionally reduced peak value of said voltage; comparing said voltage to said proportionally reduced peak value of said voltage; and producing a delayed commutation signal.
Claim 55
Dependent Claim
25 words
The method of claim 51 wherein said peak value of said voltage is proportionally reduced to approximately one-half of said peak value of said voltage.
Claim 56
Independent Claim
64 words
A method for providing commutation delay comprising the steps of: detecting a back-EMF pulse; producing a voltage proportional to the time elapsed since the back-EMF pulse occurred; proportionally reducing said voltage to produce a proportionally reduced voltage; holding a peak value of said proportionally reduced voltage; comparing said voltage to said peak value of said proportionally reduced voltage; and producing a delayed commutation signal.
Claim 57
Independent Claim
64 words
A method for providing commutation delay comprising the steps of: detecting a back-EMF pulse; producing a voltage proportional to the time elapsed since the back-EMF pulse occurred; proportionally reducing said voltage to produce a proportionally reduced voltage; holding a peak value of said proportionally reduced voltage; comparing said voltage to said peak value of said proportionally reduced voltage; and producing a delayed commutation signal.
Claim 58
Dependent Claim
17 words
The method of claim 53 wherein said voltage is proportionally reduced to approximately one-half of said voltage.
Claim 59
Independent Claim
62 words
A method for providing commutation delay comprising the steps of: detecting a back-EMF pulse; producing a voltage proportional to the time elapsed since the back-EMF pulse occurred; holding a peak value of said voltage; proportionally increasing said voltage to produce a proportionally increased voltage; comparing said proportionally increased voltage to said peak value of said voltage; and producing a delayed commutation signal.
Claim 60
Independent Claim
62 words
A method for providing commutation delay comprising the steps of: detecting a back-EMF pulse; producing a voltage proportional to the time elapsed since the back-EMF pulse occurred; holding a peak value of said voltage; proportionally increasing said voltage to produce a proportionally increased voltage; comparing said proportionally increased voltage to said peak value of said voltage; and producing a delayed commutation signal.
Claim 61
Dependent Claim
16 words
The method of claim 55 wherein said voltage is proportionally increased to approximately twice said voltage.
References Cited (Backward Citations)
US4686437A
Cited
US4442386A
Cited
US4551708A
Cited
US4633150A
Cited
US5019756A
Cited
US5028852A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-06 | 1997-12-06 | 1998-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-06 | 2001-12-06 | 2002-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-06 | 2005-12-06 | 2006-06-07 | $7700.00 | Window Closed / Lapsed |