US5317248A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Micro-controller based PWM waveform generation for a multiple phase AC machine
Assignee: Delco Electronics LLC
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Filing: 1992-11-12
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Granted: 1994-05-31
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Expires: 2012-11-12
Abstract
Abstract A multi-processor AC motor control system having a timer processor which generates multiple synchronized PWM waveforms while minimizing software latency effects. The timer processor generates a 50% PWM duty cycle sync signal at the PWM frequency, creating a logic level transition (leading edge) in each PWM period. At each such transition, the timer processor interrupts the host processor for the purpose of updating a multi-byte timer data register with PWM on-time data stored in nonvolatile memory as a function of machine position and requested current. A separate timer channel is provided for each PWM waveform to be generated, and the timer processor sets off-to-on and on-to-off transitions of each waveform in accordance with the updated PWM on-time data such that respective off-to-on and on-to-off transitions in each waveform are centered about the leading edges of the sync signal. If the on-time is 0% or 100%, the timer processor overrides the normal instruction set and forces the logic state of the waveforms to a full-off or full-on logic state.
Inventors
- 👤 Daniel E. Utley
- 👤 Kevin M. Deasy
- 👤 Gordon D. Cheever, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:40
CPC Classifications
H; H02; H02P; H02P6/00; H02P6/08; H02P6/085; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/5387; H02M7/53871; H02M7/53873
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
180 words
In a control system for a multiple phase AC machine including an array of switching devices defining an inverter, a timer data register for storing PWM on-time data for respective switching devices of said inverter, a host processor interruptable to update said PWM on-time data based on a machine position encoder signal and a requested machine current, and a timer processor for generating conduction control signals for the switching devices of said inverter based on the PWM on-time data stored in said timer data register, a method of operation for said timer processor comprising the steps of: generating a sync signal having leading edges occurring once per PWM cycle; interrupting said host CPU at successive leading edges to initiate periodic updating of the PWM on-time data stored in said timer data register; setting off-to-on and on-to-off transitions of said conduction control signals in accordance with the updated PWM on-time data such that said transitions are centered about a succeeding leading edge of said sync signal; and controlling the switching devices of said inverter in accordance with respective conduction control signals.
Claim 2
Dependent Claim
180 words
In a control system for a multiple phase AC machine including an array of switching devices defining an inverter, a timer data register for storing PWM on-time data for respective switching devices of said inverter, a host processor interruptable to update said PWM on-time data based on a machine position encoder signal and a requested machine current, and a timer processor for generating conduction control signals for the switching devices of said inverter based on the PWM on-time data stored in said timer data register, a method of operation for said timer processor comprising the steps of: generating a sync signal having leading edges occurring once per PWM cycle; interrupting said host CPU at successive leading edges to initiate periodic updating of the PWM on-time data stored in said timer data register; setting off-to-on and on-to-off transitions of said conduction control signals in accordance with the updated PWM on-time data such that said transitions are centered about a succeeding leading edge of said sync signal; and controlling the switching devices of said inverter in accordance with respective conduction control signals.
Claim 3
Dependent Claim
97 words
The control method set forth in claim 1, wherein the conduction control signals for each machine phase are developed by a controlled timer device, and the step of setting off-to-on and on-to-off conduction signal transitions for each machine phase, includes the steps of: retrieving an updated Pwm on-time from said timer data register; and configuring a respective timer device so that said off-to-on transition is timed to occur (on-time)/2 prior to said succeeding leading edge of said sync signal, and said on-to-off transition is timed to occur (on-time)/2 after said succeeding leading edge of said sync signal.
Claim 4
Dependent Claim
79 words
The control method set forth in claim 1, wherein the setting of said off-to-on transitions is initiated at each on-to-off transition which precedes said succeeding leading edge of said sync signal, and includes the steps of: retrieving an updated PWM on-time from said timer register; dividing said retrieved PWM on-time into equal half periods; and for each conduction control signal, timing said off-to-on transition to occur one half period prior to said succeeding leading edge of said sync signal.
Claim 5
Dependent Claim
59 words
The control method set forth in claim 3, wherein the setting of said on-to-off transitions is initiated at each off-to-on transition which precedes said succeeding leading edge of said sync signal, and includes the step, for each conduction control signal, of: timing said on-to-off transition to occur one half period after said succeeding leading edge of said sync signal.
Claim 6
Dependent Claim
65 words
The control method set forth in claim 1, wherein the steps performed by said timer processor result in a latency period during which said off-to-on transitions cannot be accurately set, and the control method includes the steps of: detecting a predetermined high duty ratio operating condition; and forcing an immediate off-to-on transition of said conduction control signals in response to the detection of such condition.
Claim 7
Dependent Claim
65 words
The control method set forth in claim 1, wherein the steps performed by said timer processor result in a latency period during which said on-to-off transitions cannot be accurately set, and the control method includes the steps of: detecting a predetermined low duty ratio operating condition; and forcing an immediate on-to-off transition of said conduction control signals in response to the detection of such condition.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-30 | 1997-11-29 | 1998-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-30 | 2001-11-29 | 2002-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-30 | 2005-11-29 | 2006-05-31 | $7700.00 | Window Closed / Lapsed |