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US5790831A
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VL-bus/PCI-bus bridge
Assignee: OPTi Inc
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Filing: 1996-09-18
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Granted: 1998-08-04
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Expires: 2016-09-18
Abstract
Abstract A PCI-bus is added to a VESA local bus (VL-bus) computer system using a VL-bus/PCI-bus bridge. The VL-bus/PCI-bus bridge claims a VL-bus cycle by asserting LDEV# to the VL-bus/system-bus bridge. If no other VL-bus device claims the cycle as well, then the VL-bus/PCI-bus bridge translates the cycle onto the PCI-bus and awaits a response from a PCI device. If no PCI device claims a cycle by the PCI-bus device claiming deadline, then the VL-bus/PCI-bus bridge asserts BOFF# to the host and suppresses its assertion of LDEV# when the host repeats the cycle on the VL-bus. The VL-bus/system-bus bridge therefore can translate the repetition of the cycle onto the system bus. When asserting BOFF# to the host, the VL-bus/PCI-bus bridge also asserts the VL-bus device ready signal LRDY# after assertion of BOFF# and releases LRDY# before releasing BOFF#. The VL-bus controller does not receive BOFF# necessarily, but responds to LRDY# by asserting RDYRTN# onto the VL-bus, thereby signifying to all other VL-bus devices that the VL-bus cycle has ended and permitting them to restart their state machines in anticipation of a new VL-bus cycle. The host ignores RDYRTN# while, and only while, BOFF# is asserted.
Inventors
- 👤 Fong Lu (David) Lin
- 👤 Cherng-Yeuan (Henry) Tsay
- 👤 David H. Doan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:40
CPC Classifications
G; G06; G06F; G06F21/00; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/405; G06F2207/00; G06F2207/72; G06F2207/7219
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
370 words
A method for bridging a first bus (VL-bus) cycle to a second bus (PCI-bus), in a system including a first bus (VL-bus) having first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#) and a first bus device claiming signal line (LDEVO#), said system further including said second bus (PCI-bus) and a third bus (system bus), said second bus having cycle definition lines (e.g. C/BE#, FRAME#) and a second bus device claiming line (DEVSEL#), for use with a first bus (VL-bus) host (102) defining said first bus cycle by asserting first bus cycle definition signals on said first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#), said first bus host further having a back-off input line (BOFF#) and repeating said first bus cycle after detecting assertion of a back-off signal on said back-off input line, for use further with a first-bus/third-bus (VL-bus/system-bus) bridge coupled to receive said first bus cycle definition signals, said first-bus/third-bus bridge defining a cycle on said third bus in response to certain combinations of said first bus cycle definition signals only if no first bus device claiming signal (LDEVO#) is asserted before a predetermined first bus device claiming deadline following detection by said first-bus/third-bus bridge of an asserted first bus cycle start signal (ADS#) (e.g. R/W#, M/IO#, D/C#, VA, BE#), said method comprising the steps of: asserting said first bus device claiming signal (LDEVO#) prior to said first bus device claiming deadline, in response to a first assertion of said first bus cycle start signal (ADS#), at the time of which the signals on said first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#), being a first valid first bus cycle definition, are within a predetermined set of first bus cycle definitions; defining a cycle on said second bus (PCI-bus) in response to said first assertion of said first bus cycle start signal (ADS#) by asserting second bus cycle definition signals on said second bus cycle definition lines (e.g. C/BE#, FRAME#); and asserting said back-off signal (BOFF#) if no second bus device claiming signal (DEVSEL#) is asserted before a predetermined second bus device claiming deadline following said assertion of second bus cycle definition signals on said second bus cycle definition lines.
Claim 2
Dependent Claim
29 words
A method according to claim 1, wherein said first bus is a VL-bus, said second bus is a PCI-bus and said third bus is an IBM PC/AT-compatible system bus.
Claim 3
Dependent Claim
29 words
A method according to claim 2, wherein said system bus comprises in combination an X-bus and a bus selected from the group consisting of an ISA-bus and an EISA-bus.
Claim 4
Dependent Claim
34 words
A method according to claim 2, wherein said first bus cycle definition lines include R/W#, M/IO#, D/C#, VA and BE# signal lines, and wherein said second bus cycle definition lines include C/BE# and FRAME#.
Claim 5
Dependent Claim
49 words
A method according to claim 1, wherein said first bus host comprises at least one element selected from the group consisting of a CPU, a cache memory controller and a bridge bridging said first bus (VL-bus) with a fourth bus (host-bus) different from said first, second and third buses.
Claim 6
Dependent Claim
68 words
A method according to claim 1, for use with at least one first bus device each coupled to receive said first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#) and having a respective first bus device claiming output (LDEV<x>#), further comprising the step of asserting said first bus device claiming signal (LDEVO#) in response to assertion of one of said first bus device claiming outputs (LDEV(x)#).
Claim 7
Dependent Claim
79 words
A method according to claim 1, wherein said predetermined set of first bus cycle definitions excludes all first bus cycles which match a programmable indication of first bus cycles intended for devices on said first bus (VL-bus), further comprising, prior to said step of asserting said first bus device claiming signal (LDEVO#), the step of comparing said first valid first bus cycle definition signals with said programmable indication of first bus cycles intended for devices on said first bus.
Claim 8
Dependent Claim
78 words
A method according to claim 1, wherein said predetermined set of first bus cycle definitions excludes all first bus cycles which match a programmable indication of first bus cycles intended for devices on said third bus (system bus), further comprising, prior to said step of asserting said first bus device claiming signal (LDEVO#), the step of comparing said first bus cycle definition signals with said programmable indication of first bus cycles intended for devices on said third bus.
Claim 9
Dependent Claim
80 words
A method according to claim 1, wherein said predetermined set of first bus cycle definitions excludes all first bus cycles which match a predefined indication of first bus cycles not intended for devices on said second bus (PCI-bus), further comprising, prior to said step of asserting said first bus device claiming signal (LDEVO#), the step of comparing said first valid first bus cycle definition signals with said indication of first bus cycles not intended for devices on said second bus.
Claim 10
Dependent Claim
136 words
A method according to claim 1, wherein said first bus host comprises a first-bus/fourth-bus bridge bridging said first bus with a fourth bus (host bus) different from said first, second and third buses, said first-bus/fourth-bus bridge defining a plurality of said first bus (VL-bus) cycles in response to each fourth bus (host-bus) cycle detected by said first-bus/fourth-bus bridge on said fourth bus, further comprising the step of asserting said first bus device claiming signal (LDEVO#) prior to said first bus device claiming deadline, in response to each assertion of said first-bus cycle start signal prior to said first assertion of said cycle start signal, and at the time of which the signals on said first bus (VL-bus) cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#), are within a predetermined set of first bus cycle definitions.
Claim 11
Dependent Claim
198 words
A method according to claim 1, further comprising the steps of: after assertion of said back-off signal in said step of asserting said back-off signal, in response to a second assertion of said first bus cycle start signal (ADS#), determining whether a second valid first bus cycle definition then asserted on said first bus (VL-bus) cycle definition lines is a repetition of said first valid first bus cycle definition; asserting said first bus device claiming signal (LDEVO#) prior to said first bus device claiming deadline, in response to said second assertion of said first bus cycle start signal, only if said second valid first bus cycle definition is not a repetition of said first valid first bus cycle definition; and defining a cycle on said second bus (PCI-bus) in response to said second assertion of first bus cycle start signal by asserting second bus cycle definition signals on said second bus cycle definition lines (e.g. C/BE#, FRAME#), only if said second valid first bus cycle definition is not a repetition of said first valid first bus cycle definition and only if said second valid first bus cycle definition is within said predetermined set of first bus cycle definitions.
Claim 12
Dependent Claim
145 words
A method according to claim 11, wherein said first bus host comprises a first-bus/fourth-bus bridge bridging said first bus with a fourth bus (host bus) different from said first, second and third buses, said first-bus/fourth-bus bridge defining a plurality of said first bus (VL-bus) cycles in response to each fourth bus (host-bus) cycle detected by said first-bus/fourth-bus bridge on said fourth bus, wherein said step of asserting said first bus device claiming signal (LDEVO#) in response to said second assertion of said first bus cycle start signal, asserts said first bus device claiming signal (LDEVO#) in response to said second assertion of said first bus cycle start signal only if said second valid first bus cycle definition is not one of the plurality of first bus (VL-bus) cycles defined by said first-bus/fourth-bus bridge which includes said repetition of said first valid first bus cycle definition.
Claim 13
Dependent Claim
128 words
A method according to claim 1, wherein said first bus (VL-bus) host (102) after asserting a first bus cycle start signal, withholds further assertions of said first bus cycle start signal until after detection by said first bus host (102) of a first bus (VL-bus) ready return signal (e.g. RDYRTN#), said first-bus/third-bus (VL-bus/system-bus) bridge asserting said ready return signal (e.g. RDYRTN#) in response to detection by said first-bus/third-bus (VL-bus/system-bus) bridge of a first bus (VL-bus) device ready signal (e.g. LRDY#), further comprising the step of asserting said first bus device ready signal (e.g. LRDY#) if no second bus device claiming signal (DEVSEL#) is asserted before said predetermined second bus device claiming deadline following said assertion of second bus cycle definition signals on said second bus cycle definition lines.
Claim 14
Dependent Claim
63 words
A method according to claim 13, wherein said back-off signal (BOFF#) is asserted in said step of asserting said back-off signal, before said first bus device ready signal (e.g. LRDY#) is asserted in said step of asserting said first bus device ready signal, further comprising the steps of: unasserting said first bus device ready signal (LRDY#); and subsequently unasserting said back-off signal (BOFF#).
Claim 15
Dependent Claim
31 words
A method according to claim 14, further comprising the step of unasserting said first bus device claiming signal (LDEVO#) after detection of said first bus ready return signal (e.g. RDYRTN#) asserted.
Claim 16
Independent Claim
247 words
A method for responding to a first bus (VL-bus) cycle, for use with a first bus (VL-bus) host (102) defining said first bus cycle by asserting first bus cycle definition signals on first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#) and asserting a first bus cycle start signal (ADS#), said first bus host withholding any further assertion of said first bus cycle start signal until detecting a first bus (VL-bus) ready signal (RDYRTN#) subsequent to said assertion of first bus cycle start signal, or a first bus back-off (BOFF#) signal, whichever occurs earlier, said first bus host repeating said first bus cycle after detecting said back-off signal (BOFF#), for use further with a first bus controller which asserts said first bus ready signal (RDYRTN#) in response to detecting assertion of a local device ready signal (LRDY#), comprising, after assertion by said first bus host of a given first bus cycle start signal and no later than any assertion of said first bus start signal subsequent to said given first bus cycle start signal, the steps of: asserting said back-off signal (BOFF#) in response to a first clock pulse; asserting said local device ready signal (LRDY#) in response to a second clock pulse after said first clock pulse; negating said local device ready signal (LRDY#) in response to a third clock pulse after said second clock pulse; and negating said back-off signal (BOFF#) in response to a fourth clock pulse after said third clock pulse.
Claim 17
Independent Claim
247 words
A method for responding to a first bus (VL-bus) cycle, for use with a first bus (VL-bus) host (102) defining said first bus cycle by asserting first bus cycle definition signals on first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#) and asserting a first bus cycle start signal (ADS#), said first bus host withholding any further assertion of said first bus cycle start signal until detecting a first bus (VL-bus) ready signal (RDYRTN#) subsequent to said assertion of first bus cycle start signal, or a first bus back-off (BOFF#) signal, whichever occurs earlier, said first bus host repeating said first bus cycle after detecting said back-off signal (BOFF#), for use further with a first bus controller which asserts said first bus ready signal (RDYRTN#) in response to detecting assertion of a local device ready signal (LRDY#), comprising, after assertion by said first bus host of a given first bus cycle start signal and no later than any assertion of said first bus start signal subsequent to said given first bus cycle start signal, the steps of: asserting said back-off signal (BOFF#) in response to a first clock pulse; asserting said local device ready signal (LRDY#) in response to a second clock pulse after said first clock pulse; negating said local device ready signal (LRDY#) in response to a third clock pulse after said second clock pulse; and negating said back-off signal (BOFF#) in response to a fourth clock pulse after said third clock pulse.
Claim 18
Dependent Claim
29 words
A method according to claim 16, further comprising the step of detecting said first bus ready signal (RDYRTN#) no later than said step of negating said back-off signal (BOFF#).
Claim 19
Dependent Claim
145 words
A method according to claim 16, for use further with a first-bus/third-bus (VL-bus/system-bus) bridge coupled to receive said first bus cycle definition signals, said first-bus/third-bus bridge defining a cycle on said third bus in response to certain combinations of said first bus cycle definition signals only if said first-bus/third-bus bridge fails to detect a first bus device claiming signal (LDEVO#) before a predetermined first bus device claiming deadline following detection by said first-bus/third-bus bridge of an asserted first bus cycle start signal(ADS#), further comprising the steps of: asserting said first bus device claiming signal (LDEVO#) before said first bus device claiming deadline in response to detecting said given first bus cycle start signal, and before said step of asserting said back-off signal (BOFF#); and negating said first bus device claiming signal (LDEVO#) no earlier than said step of negating said local device ready signal (LRDY#).
Claim 20
Independent Claim
204 words
A method for bridging a first bus (VL-bus) cycle to a second bus (PCI-bus), in a system including a first bus (VL-bus) having first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#), said system further including said second bus (PCI-bus), said second bus having second bus cycle definition lines (e.g. C/BE#, FRAME#), for use with a first bus (VL-bus) master (102) defining said first bus cycle by asserting first bus cycle definition signals on said first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#), said first bus master further having a back-off input line (BOFF#) which causes said first bus master to repeat said first bus cycle after detecting assertion of a back-off signal on said back-off input line, said method comprising the steps of: defining a cycle on said second bus (PCI-bus) in response to a first assertion of said first bus cycle start signal (ADS#) by asserting second bus cycle definition signals on said second bus cycle definition lines (e.g. C/BE#, FRAME#); and asserting said back-off signal (BOFF#) in response to a predefined event occurring on said second bus (PCI-bus) in response to said assertion of second bus cycle definition signals on said second bus cycle definition lines.
Claim 21
Independent Claim
204 words
A method for bridging a first bus (VL-bus) cycle to a second bus (PCI-bus), in a system including a first bus (VL-bus) having first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#), said system further including said second bus (PCI-bus), said second bus having second bus cycle definition lines (e.g. C/BE#, FRAME#), for use with a first bus (VL-bus) master (102) defining said first bus cycle by asserting first bus cycle definition signals on said first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#), said first bus master further having a back-off input line (BOFF#) which causes said first bus master to repeat said first bus cycle after detecting assertion of a back-off signal on said back-off input line, said method comprising the steps of: defining a cycle on said second bus (PCI-bus) in response to a first assertion of said first bus cycle start signal (ADS#) by asserting second bus cycle definition signals on said second bus cycle definition lines (e.g. C/BE#, FRAME#); and asserting said back-off signal (BOFF#) in response to a predefined event occurring on said second bus (PCI-bus) in response to said assertion of second bus cycle definition signals on said second bus cycle definition lines.
Claim 22
Dependent Claim
43 words
A method according to claim 19, wherein said predefined event is defined at least in part by expiration of a predefined time period that begins in response to said assertion of second bus cycle definition signals on said second bus cycle definition lines.
Claim 23
Dependent Claim
26 words
A method according to claim 20, wherein said predefined event is defined further by non-detection of a predefined signal before expiration of said predefined time period.
Claim 24
Dependent Claim
42 words
A method according to claim 19, wherein said predefined event occurs on said second bus without any intervening event occurring on said second bus in response to said assertion of second bus cycle definition signals on said second bus cycle definition lines.
Claim 25
Dependent Claim
73 words
A method according to claim 19, wherein said second bus further has a second bus device claiming signal line (DEVSEL#), and wherein said predefined event is defined at least in part by non-assertion of a second bus device claiming signal on said second bus device claiming signal line (DEVSEL#) before a predetermined second bus device claiming deadline following said assertion of second bus cycle definition signals on said second bus cycle definition lines.
Claim 26
Dependent Claim
182 words
A method according to claim 23, wherein said first bus further has a first bus device claiming signal line (LDEVO#), and wherein at the time of said first assertion of said first bus cycle start signal (ADS#) the signals on said first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#) are within a predetermined set of first bus cycle definitions, for use further with a third bus (system bus) and a first-bus/third-bus (VL-bus/system-bus) bridge coupled to receive said first bus cycle definition signals, said first-bus/third-bus bridge defining a cycle on said third bus in response to certain combinations of said first bus cycle definition signals only if no first bus device claiming signal (LDEVO#) is asserted before a predetermined first bus device claiming deadline following detection by said first-bus/third-bus bridge of an asserted first bus cycle start signal (ADS#) (e.g. R/W#, M/IO#, D/C#, VA, BE#), further comprising the step of asserting said first bus device claiming signal (LDEVO#) prior to said first bus device claiming deadline, in response to said first assertion of said first bus cycle start signal (ADS#).
Claim 27
Dependent Claim
159 words
A method according to claim 19, wherein the signals on said first bus cycle definition lines at the time of said first assertion of said first bus cycle start signal (ADS#) define a first valid first bus cycle, further comprising the steps of: after assertion of said back-off signal in said step of asserting said back-off signal, in response to a second assertion of said first bus cycle start signal (ADS#), determining whether a second valid first bus cycle defined by signals then asserted on said first bus (VL-bus) cycle definition lines is a repetition of said first valid first bus cycle; and defining a cycle on said second bus (PCI-bus) in response to said second assertion of first bus cycle start signal by asserting second bus cycle definition signals on said second bus cycle definition lines (e.g. C/BE#, FRAME#), only if said second valid first bus cycle is not a repetition of said first valid first bus cycle.
Claim 28
Dependent Claim
53 words
A method according to claim 19, for use further with a third bus (ISA bus) having third bus cycle definition lines, further comprising a step of defining a cycle on said third bus (ISA-bus) in dependence upon said first bus cycle, after said step of defining a cycle on said second bus (PCI-bus).
Claim 29
Dependent Claim
28 words
A method according to claim 26, wherein said step of defining a cycle on said third bus (ISA-bus) occurs after said step of asserting said back-off signal (BOFF#).
Claim 30
Dependent Claim
202 words
Apparatus for bridging a first bus (VL-bus) cycle to a second bus (PCI-bus), in a system including a first bus (VL-bus) having first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#), said system further including said second bus (PCI-bus), said second bus having second bus cycle definition lines (e.g. C/BE#, FRAME#), for use with a first bus (VL-bus) master (102) defining said first bus cycle by asserting first bus cycle definition signals on said first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#), said first bus master further having a back-off input line (BOFF#) and repeating said first bus cycle after detecting assertion of a back-off signal on said back-off input line, comprising: second bus interface logic which defines a cycle on said second bus (PCI-bus) in response to a first assertion of said first bus cycle start signal (ADS#) by asserting second bus cycle definition signals on said second bus cycle definition lines (e.g. C/BE#, FRAME#); and first bus interface logic which asserts said back-off signal (BOFF#) in response to a predefined event occurring on said second bus (PCI-bus) in response to said assertion of second bus cycle definition signals on said second bus cycle definition lines.
Claim 31
Dependent Claim
202 words
Apparatus for bridging a first bus (VL-bus) cycle to a second bus (PCI-bus), in a system including a first bus (VL-bus) having first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#), said system further including said second bus (PCI-bus), said second bus having second bus cycle definition lines (e.g. C/BE#, FRAME#), for use with a first bus (VL-bus) master (102) defining said first bus cycle by asserting first bus cycle definition signals on said first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#), said first bus master further having a back-off input line (BOFF#) and repeating said first bus cycle after detecting assertion of a back-off signal on said back-off input line, comprising: second bus interface logic which defines a cycle on said second bus (PCI-bus) in response to a first assertion of said first bus cycle start signal (ADS#) by asserting second bus cycle definition signals on said second bus cycle definition lines (e.g. C/BE#, FRAME#); and first bus interface logic which asserts said back-off signal (BOFF#) in response to a predefined event occurring on said second bus (PCI-bus) in response to said assertion of second bus cycle definition signals on said second bus cycle definition lines.
Claim 32
Dependent Claim
72 words
Apparatus according to claim 28, wherein said second bus further has a second bus device claiming signal line (DEVSEL#), and wherein said predefined event is defined at least in part by non-assertion of a second bus device claiming signal on said second bus device claiming signal line (DEVSEL#) before a predetermined second bus device claiming deadline following said assertion of second bus cycle definition signals on said second bus cycle definition lines.
Claim 33
Dependent Claim
180 words
Apparatus according to claim 29, wherein said first bus further has a first bus device claiming signal line (LDEVO#), and wherein at the time of said first assertion of said first bus cycle start signal (ADS#) the signals on said first bus cycle definition lines (e.g. R/W#, M/IO#, D/C#, VA, BE#) are within a predetermined set of first bus cycle definitions, for use further with a third bus (system bus) and a first-bus/third-bus (VL-bus/system-bus) bridge coupled to receive said first bus cycle definition signals, said first-bus/third-bus bridge defining a cycle on said third bus in response to certain combinations of said first bus cycle definition signals only if no first bus device claiming signal (LDEVO#) is asserted before a predetermined first bus device claiming deadline following detection by said first-bus/third-bus bridge of an asserted first bus cycle start signal (ADS#) (e.g. R/W#, M/IO#, D/C#, VA, BE#), further comprising circuitry which asserts said first bus device claiming signal (LDEVO#) prior to said first bus device claiming deadline, in response to said first assertion of said first bus cycle start signal (ADS#).
Claim 34
Dependent Claim
175 words
Apparatus according to claim 28, wherein the signals on said first bus cycle definition lines at the time of said first assertion of said first bus cycle start signal (ADS#) define a first valid first bus cycle, further comprising a repetition detector which, after assertion of said back-off signal by said first bus interface logic in response to said predefined event, in response to a second assertion of said first bus cycle start signal (ADS#), determines whether a second valid first bus cycle defined by signals then asserted on said first bus (VL-bus) cycle definition lines is a repetition of said first valid first bus cycle, and wherein said second bus interface logic further defines a cycle on said second bus (PCI-bus) in response to said second assertion of first bus cycle start signal by asserting second bus cycle definition signals on said second bus cycle definition lines (e.g. C/BE#, FRAME#), only if said repetition detector determines that said second valid first bus cycle is not a repetition of said first valid first bus cycle.
Claim 35
Dependent Claim
56 words
Apparatus according to claim 28, for use further with a third bus (ISA bus) having third bus cycle definition lines, further comprising third bus interface logic which defines a cycle on said third bus (ISA-bus) in dependence upon said first bus cycle, after said second bus interface logic defines a cycle on said second bus (PCI-bus).
Claim 36
Dependent Claim
30 words
Apparatus according to claim 32, wherein said third bus interface logic defines said cycle on said third bus (ISA-bus) after said first bus interface logic asserts said back-off signal (BOFF#).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-03 | 2002-02-02 | 2002-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-03 | 2006-02-02 | 2006-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-03 | 2010-02-02 | 2010-08-04 | $7700.00 | Window Closed / Lapsed |