Vme-multibus ii interface adapter for protocol conversion and for monitoring and discriminating accesses on the multibus ii system bus

Claim 1

An interface adapter having a VME bus interface and a MULTIBUS II interface for interconnecting an electronic unit having said VME bus interface with a MULTIBUS II system bus, through said VME bus interface and said MULTIBUS II interface, respectively; said interface adapter including a circuit board comprising logic circuits for converting interface signals conforming to a protocol of said VME bus interface into interface signals conforming to a protocol of said MULTIBUS II interface and vice versa, said logic circuits comprising: first logic means having one of an active state and an inactive state, said first logic means, when in said active state, requesting and obtaining access to said system bus for said electronic unit and when in said inactive state, asserting a signal of no access to said system bus; and second logic means, connected to said first logic means, receiving said no access signal from said first logic means and control signals from said system bus for monitoring accesses to said system bus and discriminating said accesses between ones of said accesses which have been requested by said first logic means and ones of said accesses which have not been requested by said first logic means; said second logic means, upon detection of any one of said accesses not requested by said first logic means, transferring to said VME bus interface operation requests received at said MULTIBUS II interface, concurrently with said detected access; said second logic means, upon receipt of a first response signal at said VME interface from said electronic unit in response to said operation requests, generating a second response signal and asserting said second response signal on said system bus, said second response signal being one of said converted interface signals; and said second logic means monitoring said system bus for an end of transfer signal and, upon detection of said end of transfer signal asserted on said system bus, resuming a wait monitoring state.