An input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the buses

Claim 2

In a device, adapted for attachment to a bus, including an interface section and a main section, said interface section adapted to join said bus to said main section of said device, said interface section comprising: address and data communication means attached to the main section of said device for conducting address information or data information between said bus and said main section of said device; command and status communication means attached to the main section of said device for conducting command information or status information between said bus and said main section of said device; and origin and destination communication means attached to the main section of said device for conducting origin address information or destination address information between said bus and said main section of said device.

Claim 3

The interface section of claim 1, further comprising: control communication means attached to the main section of said device for conducting control information between said bus and said main section of said device.

Claim 4

The interface section of claim 1, wherein said address and data communication means conducts key information and main memory storage address in­formation between said bus and said main section of said device during a select cycle of a storage write to storage operation or a storage read from storage operation, said address and data communication means conducting a word of data between said bus and said main section of said device during a data cycle of said storage write to storage operation or said storage read from storage operation.

Claim 5

The interface section of claim 3, wherein said command and status communication means conducts write command information and a number of bytes of data during a select cycle and completion status during a subsequent data cycle of a storage write to storage operation, said command and status communicat­ion means conducting read command information and a number of bytes of data during a select cycle and completion status during a subsequent data cycle of a storage read from storage operation.

Claim 6

The interface section of claim 1, wherein said address and data communication means conducts data information between said bus and said main section of said device during a unit write operation or a unit read operation.

Claim 7

The interface section of claim 5, wherein said command and status communication means conducts a write command during a select cycle of a unit write operation and a read command during a select cycle of a unit read operation, said command and status communication means conducting a completion status during a subsequent data cycle of the unit write operation and the unit read operation.

Claim 8

The interface section of claim 2, wherein said address and data communication means conducts said control information during a select cycle of a unit write direct operation and a unit read direct operation and conducts data during a data cycle of said unit write direct operation and said unit read direct operation.

Claim 9

The interface section of claim 7, wherein said command and status communication means conducts a write command during a select cycle of a unit write direct operation and conducts a completion status during a data cycle of the unit write direct operation.

Claim 10

The interface section of claim 1, wherein: said address and data communication means conducts data during a data cycle of a message acceptance operation; said origin and destination communication means conducts an address of said device during said data cycle of said message acceptance operation; and said command and status communication means conducts a completion status following the conducting of said data via said address and data communication means during said data cycle of said message acceptance operation.

Claim 11

The interface section of claim 2, wherein said control communication means comprises: tag communication means for conducting a first portion of said control information between said bus and said main section of said device, said tag communication means including, a master steering signal line means for conducting control information indicating possession of said bus, a master select signal line means for conducting control information acknowledging the placement of data on said bus and the validity of said data, and a ready signal line means for conducting control information acknowledging receipt of said data placed on said bus and communicating a possible intent to conduct further data via said bus.

Claim 12

The interface section of claim 10, wherein said control communication means further comprises: card select communication means for conducting a second portion of said control information; and board select communication means for conducting a third portion of said control information, said address and data communication means conducting said second portion of said control information associated with the card select communication means and conducting said third portion of said control information associated with the board select communication means during a select cycle of a unit write direct operation and a unit read direct operation.

Claim 15

The method of claim 12, wherein, during a select cycle of a write to storage operation, said first part of said information includes key information and starting main store address information, the transmitting step including the step of transmitting said key information and said starting main store address information from said IOBU to said controller device via said address data bus of said first bus.

Claim 16

The method of claim 13, wherein, during said select cycle of said write to storage operation, said second part of said information includes a write command and a number representing the number of bytes of data to be stored in said main store, the transmitting step including the step of transmitting said write command and said number of bytes of data from said IOBU to said controller device via said command status bus of said first bus.

Claim 17

The method of claim 12, wherein, during a data cycle of a write to storage operation, said first part of said information includes a word of data, the transmitting step including the step of transmitting said word of data from said IOBU to said controller device via said address data bus.

Claim 18

The method of claim 15, wherein, during said data cycle of said write to storage operation, said third part of said information includes an address of said IOBU, the transmitting step including the step of transmitting said address of said IOBU from said IOBU to said controller device via said origin destination bus.

Claim 19

The method of claim 12, wherein, during a select cycle of a read from storage operation, said first part of said information includes key information and starting main store address information, the transmitting step comprising the step of trans­mitting said key information and said starting main store address information from said IOBU to said controller device via said address data bus.

Claim 20

The method of claim 17, wherein, during the select cycle of the read from storage operation, said second part of said information includes a read command and a number representing the number of bytes of data to be read from said main store, the transmitting step including the step of transmitting the read command and the number representing the number of bytes of data from said IOBU to said controller device via said command status bus.

Claim 21

The method of claim 12, wherein, during a data cycle of a read from storage operation, said third part of said information includes an address of said IOBU, the transmitting step including the step of trans­mitting said address of said IOBU from said IOBU to said controller device via said origin destination bus of said first bus.

Claim 22

The method of claim 19, wherein said controller device generates a storage command and receives a word of data from said main store in response thereto, said controller device temporarily buffer­ing said word of data therein; and wherein during the data cycle of the read from storage operation, said first part of said information includes said word of data, the transmitting step including the step of transmitting said word of data from said controller device to said IOBU via said address data bus of said first bus.

Claim 25

The method of claim 21, wherein, during a unit write operation, said information is transferred from said IOBU1 to said IOBU2.

Claim 26

The method of claim 22 wherein, during a data cycle of said unit write operation: the step of transmitting information comprises the step of transmitting said first part of said information and said third part of said information from said IOBU1 to said IOBU2 via said address data bus and said origin destination bus, respectively, the step of transmitting further information comprises the step of transmitting said second part of said further information from said IOBU2 to said IOBU1 via said command status bus, said first part of said information being data, said third part of said information being an address of said IOBU1, and said second part of said further information being completion status information.

Claim 27

The method of claim 21, wherein, during a unit read operation, said further information is transferred from said IOBU2 to said IOBU1.

Claim 28

The method of claim 24, wherein, during a data cycle of said unit read operation: the step of transmitting information further comprises the step of transmitting said third part of said information from said IOBU1 to said IOBU2 via said origin destination bus; and the step of transmitting further information comprises the step of transmitting said first part of said further information and said second part of said further information from said IOBU2 to said IOBU1 via said address data bus and said command status bus, respectively; said third part of said information being an address of said IOBU1, said first part of said further information being data, said second part of said further information being completion status informat­ion.

Claim 29

The method of claim 21, wherein: said bus further includes a control line group, said control line group including a first line and a second line; and during a unit write direct operation, said informat­ion is transferred from said IOBU1 to said IOBU2, said first line and said second line of said control line group selecting said IOBU2.

Claim 30

The method of claim 26, wherein, during a select cycle of said unit write direct operation: the step of transmitting information comprises the step of transmitting said first part of said information, said second part of said information and said third part of said information from said IOBU1 to said IOBU2 via said address data bus, said command status bus, and said origin destination bus, respectively, said first part of said information being data associated with said first line and said second line of said control line group, said second part of said information being a write command, and said third part of said information being an address of said IOBU2 for said write command.

Claim 31

In a device, adapted for attachment to a bus, including an interface section and a main section, said interface section being adapted to join said bus to said main section of said device, said interface section comprising: address and data communication means attached to said main section of said device for conducting address information or data information between said bus and said main section of said device; and key and status communication means attached to said main section of said device for conducting storage protection key information and status information between said bus and said main section of said device.

Claim 32

In a device, adapted for attachment to a bus, including an interface section and a main section, said interface section being adapted to join said bus to said main section of said device, said interface section comprising: address and data communication means attached to said main section of said device for conducting address information or data information between said bus and said main section of said device; and key and status communication means attached to said main section of said device for conducting storage protection key information and status information between said bus and said main section of said device.

Claim 33

The interface section of claim 28, further comprising: control communication means for conducting control information, said control information controlling a direction of data flow of said address information or said data information along said address and data communication means and controlling a direction of data flow of said key information and said status information along said key and status communication means.

Claim 34

The interface section of claim 28, wherein said address and data communication means comprises a first byte portion means, a second byte portion means, a third byte portion means, and a fourth byte portion means; and wherein, during a processor bus operation, said first byte portion means conducts command information, said second byte portion means conducts further command information, said third byte portion means conducts priority level information and address information, and said fourth byte portion means conducts further address information.

Claim 35

The interface section of claim 28, wherein said key and status communication means comprises a key bus means and a status bus means, said key bus means conducting said storage protection key information, said status bus means conducting said status information, said status information including command status information and data status information.

Claim 36

The interface section of claim 29, wherein said control communication means comprises: command time means for conducting signals which identify said device as a recipient of information which may include a first byte of command informat­ion, a second byte of further command information, a third byte of priority level information and address information, and a fourth byte of further address information; data valid means for conducting signals which indicate that said address and data communication means should be sampled for said information; acknowledge means for conducting signals which indicate that said information has been received by said device and an operation will ensue in response thereto; busy means for conducting signals which indicate that said information has been received by said device but said device is unable to complete said operation; status word means for conducting signals which indicate an error condition; and operation end means for conducting signals which indicate a completion of said operation.

Claim 39

The method of claim 33, wherein said IOIC includes a destination select register and a selector buffer, the gating step comprises the step of storing said first information from said A-register in said destination select register of said IOIC, and the clocking step comprises the step of storing said second information from said B-register in said selector buffer of said IOIC.

Claim 46

In a data processing system including a first bus for conducting commands and data, a second bus for conducting said commands and data and a buffering means interconnected between said first bus and said second bus for buffering and storing said commands and data when said commands and data are being transferred between said first bus and said second bus, said buffering means comprising: storage means for storing said data when said data is being transferred between said first bus and said second bus; first control means connected to said first bus and to said storage means for controlling the transfer of said commands and data between said first bus and said storage means; and second control means connected to said second bus, to said storage means and to said first control means for controlling the transfer of said commands and data between said second bus and said storage means.

Claim 47

In a data processing system including a first bus for conducting commands and data, a second bus for conducting said commands and data and a buffering means interconnected between said first bus and said second bus for buffering and storing said commands and data when said commands and data are being transferred between said first bus and said second bus, said buffering means comprising: storage means for storing said data when said data is being transferred between said first bus and said second bus; first control means connected to said first bus and to said storage means for controlling the transfer of said commands and data between said first bus and said storage means; and second control means connected to said second bus, to said storage means and to said first control means for controlling the transfer of said commands and data between said second bus and said storage means.

Claim 48

In the data processing system of claim 38, wherein said buffering means further comprises: second bus arbitration means connected to said first control means, said second control means, and to said second bus for determining when said buffering means may access said second bus.

Claim 49

In the data processing system of claim 38, wherein said data processing system further includes an input output interface unit (IOIU), said first bus interconnecting said IOIU to said buffering means; and wherein, during a processor bus operation of the copy type, said IOIU transmits an adaptor command time signal to said buffering means via said first bus, said adaptor command time signal indicating that a processor bus operation (PBO) command is being transmitted from said IOIU to said buffering means via said first bus, said PBO command identifying a particular register in said storage means, the particular register containing data, the PBO command requiring that the data in the particular register of said storage means be copied and transmitted to said IOIU via said first bus, said first control means of said buffering means loading said command from said first bus into said storage means, said first control means decoding said PBO command and gating said data in said particular register onto said first bus for transmission to said IOIU.

Claim 50

In the data processing system of claim 40, wherein said particular register is an MOSW register, said MOSW register including an op end bit and remaining bits; and wherein, during a processor bus operation of the move type, said first control means resets said remaining bits of said MOSW register when said op end bit of said MOSW register is active.

Claim 51

In the data processing system of claim 40, wherein, during a processor bus operation of the load message buffer register type: a further PBO command is transmitted from said IOIU to said buffering means via said first bus, said further PBO command identifying a message buffer register in said storage means and requiring that certain data from said IOIU be loaded into said message buffer register via said first bus, said first control means of said buffering means loads said further PBO command from said first bus into said storage means, said first control means decodes said further PBO command and, in response thereto, loads said data from said first bus into said message buffer register.

Claim 52

In the data processing system of claim 39, wherein said data processing system includes an input output interface unit (IOIU), said first bus interconnecting said IOIU to said buffering means.

Claim 53

In the data processing system of claim 43, wherein said storage means comprises a message buffer 1, a message buffer 2, a destination select register and a selector buffer, said data residing in said message buffer 1 and said message buffer 2, and wherein, during a unit operation processor bus operation (PBO) of the unit operation write type: said IOIU transmits a processor bus operation (PBO) command to said buffering means via said first bus, said first control means of said buffering means loads a part of said PBO command into said destination select register of said buffering means on one cycle and another part of said PBO command into said selector buffer of said buffering means on another cycle, said destination select register being connected to a command register, said selector buffer being connected to a select data buffer, said first control means decodes said PBO command and, in response thereto, moves the contents of said selector buffer to said select data buffer and the contents of said destination select register to said command register, said first control means sends a request to said second control means and, in response thereto, said second control means assumes responsibility for execution of said PBO command, said second control means transmits an access request signal to said second bus arbitration means, when said second bus is available and in response to said access request signal, said arbitration means grants to said second control means access to said second bus, during a select cycle, said second control means transmits said PBO command in said select data buffer and said command register onto said second bus, during a data cycle, said second control means transmits a part of said data in said message buffer 1 of said storage means onto said second bus, and during a subsequent data cycle, said second control means transmits another part of said data in said message buffer 2 of said storage means onto said second bus.

Claim 54

In the data processing system of claim 39, wherein: said storage means of said buffering means comprises a plurality of data buffers including a first data buffer, a second data buffer and a third data buffer, and a set of status registers; said second bus is connected, on one end, to said buffering means and, on the other end, to one or more input output bus units (IOBUs); during a unit operation message acceptance operation: one of said IOBUs requests access to said second bus via said second bus arbitration means, when granted access to said second bus, during a select cycle, the one IOBU transmits a command and message data to said buffering means via said second bus, said second control means decodes said command, stores said command in said status registers and stores said message data in said first data buffer, during a first data cycle, the one IOBU transmits more message data and address information to said buffering means, said second control means storing said more message data in said second data buffer and said address information in said status registers, during a second data cycle, the one IOBU transmits additional message data to said buffering means, said second control means storing said additional message data in said third data buffer, said first control means assumes responsibility in the performance of said unit operation message acceptance operation from said second control means, said first control means obtains access to said first bus; said first control means drives said first bus, placing a message acceptance command on said first bus, when said message acceptance command has been placed on said first bus, said first control means places the contents of said first, second, and third data buffers onto said first bus, and when the contents of said data buffers are placed on said first bus, said first control means places the contents of said status registers on said first bus.

Claim 55

In the data processing system of claim 39, wherein: said second control means of said buffering means comprises a translator unit means for translating a command from one format into another format; said storage means of said buffering means comprises address registers and data buffers; said second bus connects said buffering means to at least one input output bus unit (IOBU); and wherein, during a storage operation of the write type: said IOBU requests access to said second bus via said bus arbitration means, when granted access to said bus, said IOBU transmits a command and address information to said buffering means via said second bus, said second control means of said buffering means storing said command and address information in said address registers of said storage means; during subsequent data cycles, said IOBU transmits data to said buffering means, said second control means storing said data in said data buffers of said storage means, said translator unit means of said second control means receives said command from said address registers and converts said command into a memory command having an alternate format, said second control means restoring said memory command in said address registers, said first control means assumes responsibility for a remaining portion of said storage operation of the write type, said first control means obtains access to said first bus; said first control means places key information and the contents of said address registers on said first bus, and said first control means places the contents of said data buffers on said first bus.

Claim 56

In the data processing system of claim 39, wherein: said second control means of said buffering means comprises a translator unit means for translating a command from one format into another format; said storage means of said buffering means comprises address registers and data buffers; said second bus connects said buffering means to at least one input output bus unit (IOBU); and wherein, during a storage operation of the read type: said IOBU requests access to said second bus via said bus arbitration means, when granted access to said bus, said IOBU transmits a command and address information to said buffering means via said second bus, said second control means of said buffering means storing said command and address information in said address registers of said storage means; during subsequent data cycles, said IOBU transmits data to said buffering means, said second control means storing said data in said data buffers of said storage means, said translator unit means of said second control means receives said command from said address registers and converts said command into a memory command having an alternate format, said second control means restoring said memory command in said address registers, said first control means assumes responsibility for performing said storage operation of the read type, said first control means obtains access to said first bus; said first control means of said buffering means transmits key information and the contents of said address registers onto said first bus, a set of data being returned to said buffering means in response thereto, during subsequent data cycles, when said data is being returned to said buffering means via said first bus, said first control means receives said set of data and stores said data in said data buffers of said storage means, said second control means re-assumes responsibility for performing said storage operation of the read type, and said second control means transmits said data from said data buffers to said IOBU via said second bus.

Claim 57

In the data processing system of claim 39, wherein: said second control means comprises translator unit means for translating a command from one format into another format; said storage means comprises address registers and data buffers; said first bus connects one end of said buffering means to one end of a storage controller (SC), the other end of said SC being connected to a data cache and a memory via a storage bus; said second bus connects the other end of said buffering means to at least one input output bus unit (IOBU); and wherein, during a storage operation of the read modify write type: said IOBU requests access to said second bus via said bus arbitration means, when granted access to said bus, said IOBU transmits a command and address information to said buffering means via said second bus, said second control means of said buffering means storing said command and address information in said address registers of said storage means; during a subsequent data cycle, said IOBU transmits data to said buffering means, said second control means storing said data in an even one of said data buffers of said storage means, said translator unit means of said second control means receives said command from said address registers, converts said command into a memory command having an alternate format, and restores said memory command in said address registers, during another subsequent data cycle, said IOBU transmits more data to said buffering means, said second control means storing said more data in an odd one of said data buffers of said storage means; said first control means assumes responsibility for a remaining portion of said storage operation of the read, modify, write type; said first control means obtains access to said first bus; said first control means places key information and the contents of said address registers on said first bus; said first control means places the contents of the even and odd data buffers on said first bus; said command and address information from said address registers and said key information are stored in said SC; the data from the even and odd data buffers are stored in said SC; in said SC, said key information is compared with a reference key value; if said key information matches said reference key value, said command and address information is transmitted from said SC to said data cache via said storage bus, said command and address information determining if other data exists in said data cache, corresponding to said address, and has been modified; if said other data exists and has been modified, said data and said more data is transmitted from said SC to said data cache via said storage bus, said data and said more data modifying said other data yielding further modified data; and said further modified data is read from said data cache and written into said memory.

Claim 62

An electrical signal conducting bus structure, comprising: address and data conducting means for conducting address information or data information; command and status conducting means for conducting command information or status information; origin and destination address conducting means for conducting origin address information or destination address information; and control information conducting means for conducting control information.

Claim 63

An electrical signal conducting bus structure, comprising: address and data conducting means for conducting address information or data information; command and status conducting means for conducting command information or status information; origin and destination address conducting means for conducting origin address information or destination address information; and control information conducting means for conducting control information.

Claim 64

The bus structure of claim 51, wherein said bus is dis­posed within a computer system, said computer system performing a storage write to storage operation and a storage read from storage operation, each said operation including a select cycle and a data cycle.

Claim 65

The bus structure of claim 52, wherein said address and data conducting means conducts key information and main memory storage address information during a select cycle of a storage write to storage operation or a storage read from storage operation, said address and data conducting means conducting a word of data during a data cycle of said storage write to storage operation or said storage read from storage operation.

Claim 66

The bus structure of claim 51, wherein said bus is disposed within a computer system, said computer system performing a unit write operation and a unit read operation, each said operation including a select cycle and a data cycle, and wherein said address and data conducting means conducts data information during said unit write operation or said unit read operation.

Claim 67

The bus structure of claim 54, wherein said command and status conducting means conducts a write command during a select cycle of said unit write operation and a read command during a select cycle of said unit read operation, said command and status conducting means conducting a completion status during a subsequent data cycle of the unit write operation and the unit read operation.

Claim 68

The bus structure of claim 51, wherein said bus is disposed within a computer system, said computer system performing a unit write direct operation and a unit read direct operation, each said operation including a select cycle and a data cycle, and wherein said address and data conducting means conducts data to a destination determined in association with said control information during a select cycle of said unit write direct operation and said unit read direct operation and conducts data during a data cycle of said unit write direct operation and said unit read direct operation.

Claim 69

The bus structure of claim 51, wherein said bus is disposed within a computer system, said computer system performing a message acceptance operation, said operation including a data cycle, and wherein: said address and data conducting means conducts data during a data cycle of said message acceptance operation; said origin and destination conducting means conducts an address of a device attached to said bus during said data cycle of said message acceptance operation; and said command and status conducting means conducts a completion status following the conducting of said data via said address and data conducting means during said data cycle of said message acceptance operation.

Claim 70

The bus structure of claim 51, wherein said control information conducting means comprises: tag conducting means for conducting a first portion of said control information, said tag conducting means including, a master steering signal line means for conducting control information indicating possession of said bus, a master select signal line means for con­ducting control information acknowledging the placement of data on said bus and the validity of said data, and a ready signal line means for conducting control information acknowledging receipt of said data placed on said bus and communicat­ing a possible intent to conduct further data via said bus.