US5789319A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of dual masking for selective gap fill of submicron interconnects
Assignee: Texas Instruments Inc
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Filing: 1996-02-26
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Granted: 1998-08-04
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Expires: 2016-02-26
Abstract
Abstract A semiconductor device and method having a low-permittivity material between closely-spaced leads in order to decrease unwanted capacitance, while having a more structurally strong dielectric between widely-spaced leads where capacitance is not as critical. A metal layer 14 is deposited on a substrate 12 of a semiconductor wafer 10, where the metal layer 14 has a first region 15 and a second region 17. An insulating layer 39 is deposited on the metal layer, and the insulating layer 39 is patterned with a conductor pattern of widely-spaced leads and closely-spaced leads. Widely-spaced leads 16 are formed in the first region 15 of the metal layer 14. At least adjacent portions of closely-spaced leads 18 are formed in the second region 17 of the metal layer 14. A low-permittivity material 34 is deposited between adjacent portions of the closely-spaced leads 18. A structural dielectric layer 26 is deposited between at least the widely-spaced leads. The low-permittivity material 34 is a material with a dielectric constant of less than 3. An advantage of the invention includes improved structural strength by placing structurally weak low-permittivity material only where needed, in areas having closely-spaced leads.
Inventors
- 👤 Robert H. Havemann
- 👤 Richard A. Stoltz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:31
CPC Classifications
H; H10; H10P; H10P95/00; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/074; H10W20/077; H10W20/076; H10W20/098
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
150 words
A method for fabricating insulated leads on a semiconductor wafer, comprising the steps of: depositing a metal layer on a substrate; depositing an insulating layer on said metal layer; defining a pattern of widely-spaced leads and closely-spaced leads on said insulating layer; and utilizing a patterned resist to delineate at least regions of widely-spaced leads from at least regions of closely-spaced leads in said insulating layer and said metal layer, to allow, first deposition of low-permittivity material at least in regions of closely-spaced leads and second, deposition of structural dielectric at least in regions of widely-spaced leads, said widely-spaced leads being leads spaced apart by more than the thickness of said metal layer, said closely-spaced leads being leads spaced apart from one another by less than or equal to the thickness of said metal layer, and said low-permittivity material being a material with a dielectric constant of less than 3.
Claim 2
Independent Claim
150 words
A method for fabricating insulated leads on a semiconductor wafer, comprising the steps of: depositing a metal layer on a substrate; depositing an insulating layer on said metal layer; defining a pattern of widely-spaced leads and closely-spaced leads on said insulating layer; and utilizing a patterned resist to delineate at least regions of widely-spaced leads from at least regions of closely-spaced leads in said insulating layer and said metal layer, to allow, first deposition of low-permittivity material at least in regions of closely-spaced leads and second, deposition of structural dielectric at least in regions of widely-spaced leads, said widely-spaced leads being leads spaced apart by more than the thickness of said metal layer, said closely-spaced leads being leads spaced apart from one another by less than or equal to the thickness of said metal layer, and said low-permittivity material being a material with a dielectric constant of less than 3.
Claim 3
Independent Claim
195 words
A method for patterning a metal layer on a semiconductor wafer, comprising the steps of: depositing a metal layer on a substrate, said metal layer having a first region and a second region; depositing an insulating layer on said metal layer; depositing a resist layer on said insulating layer; patterning said resist layer to define a pattern of widely-spaced leads and closely-spaced leads in said insulating layer; removing portions of said resist layer; and then etching said insulating layer and said metal layer to form at least widely-spaced leads in said first region of said metal layer, etching said insulating layer and said metal layer to form at least closely-spaced leads in said second region of said metal layer, depositing a low-permittivity material between at least said closely-spaced leads, and then depositing a structural dielectric layer between at least said widely-spaced leads, said widely-spaced leads being leads spaced apart by more than the thickness of said metal layer, said closely-spaced leads being leads spaced apart from one another by less than or equal to the thickness of said metal layer, and said low-permittivity material being a material with a dielectric constant of less than 3.
Claim 4
Independent Claim
195 words
A method for patterning a metal layer on a semiconductor wafer, comprising the steps of: depositing a metal layer on a substrate, said metal layer having a first region and a second region; depositing an insulating layer on said metal layer; depositing a resist layer on said insulating layer; patterning said resist layer to define a pattern of widely-spaced leads and closely-spaced leads in said insulating layer; removing portions of said resist layer; and then etching said insulating layer and said metal layer to form at least widely-spaced leads in said first region of said metal layer, etching said insulating layer and said metal layer to form at least closely-spaced leads in said second region of said metal layer, depositing a low-permittivity material between at least said closely-spaced leads, and then depositing a structural dielectric layer between at least said widely-spaced leads, said widely-spaced leads being leads spaced apart by more than the thickness of said metal layer, said closely-spaced leads being leads spaced apart from one another by less than or equal to the thickness of said metal layer, and said low-permittivity material being a material with a dielectric constant of less than 3.
Claim 5
Dependent Claim
20 words
The method of claim 2 wherein said widely-spaced leads and said closely-spaced leads are formed in a single etching step.
Claim 6
Dependent Claim
21 words
The method of claim 2 wherein all of said closely-spaced leads are formed during said etching to form closely-spaced leads step.
Claim 7
Dependent Claim
22 words
The method of claim 2 wherein said low-permittivity material has a height at least equal to the height of said closely-spaced leads.
Claim 8
Dependent Claim
35 words
The method of claim 2 wherein said low-permittivity material has a height equal to at least the height of said closely-spaced metal leads plus at least 50% of said insulating layer on said closely-spaced leads.
Claim 9
Dependent Claim
23 words
The method of claim 2 and further comprising the step of depositing a passivation layer, after said etching to form metal leads step.
Claim 10
Independent Claim
182 words
A method for fabricating insulated leads on a semiconductor wafer, comprising the steps of: depositing a metal layer on a substrate; depositing an insulating layer on said metal layer; patterning a conductor pattern of widely-spaced leads and closely-spaced leads on said insulating layer and in said metal layer; depositing low-permittivity material in regions of closely-spaced leads and in regions of widely-spaced leads; applying a patterned resist to cover at least regions of closely-spaced leads and to expose low-permittivity material in at least regions of widely-spaced leads; removing said exposed low-permittivity material in at least regions of widely-spaced leads; removing said patterned resist to uncover remaining low-permittivity material in at least regions of closely-spaced leads; and depositing structural dielectric in regions of widely-spaced leads and over said remaining low-permittivity material, said widely-spaced leads being leads spaced apart by more than the thickness of said metal layer, said closely-spaced leads being leads spaced apart from one another by less than or equal to the thickness of said metal layer, and said low-permittivity material being a material with a dielectric constant of less than 3.
Claim 11
Independent Claim
182 words
A method for fabricating insulated leads on a semiconductor wafer, comprising the steps of: depositing a metal layer on a substrate; depositing an insulating layer on said metal layer; patterning a conductor pattern of widely-spaced leads and closely-spaced leads on said insulating layer and in said metal layer; depositing low-permittivity material in regions of closely-spaced leads and in regions of widely-spaced leads; applying a patterned resist to cover at least regions of closely-spaced leads and to expose low-permittivity material in at least regions of widely-spaced leads; removing said exposed low-permittivity material in at least regions of widely-spaced leads; removing said patterned resist to uncover remaining low-permittivity material in at least regions of closely-spaced leads; and depositing structural dielectric in regions of widely-spaced leads and over said remaining low-permittivity material, said widely-spaced leads being leads spaced apart by more than the thickness of said metal layer, said closely-spaced leads being leads spaced apart from one another by less than or equal to the thickness of said metal layer, and said low-permittivity material being a material with a dielectric constant of less than 3.
Claim 12
Independent Claim
244 words
A method for patterning a metal layer on a semiconductor wafer, comprising the steps of: depositing a metal layer on a substrate, said metal layer having a first region and a second region; depositing an insulating layer on said metal layer; depositing a first resist on said insulating layer; patterning said first resist to form a conductor pattern on said insulating layer; removing said first resist; covering said insulating layer over said second region of said metal layer with a second resist; etching said insulating layer over said first region of said metal layer and said first region of said metal layer to form widely-spaced leads, said widely-spaced leads having leads spaced apart by more than the thickness of said metal layer; depositing a first structural dielectric layer on said widely-spaced leads; removing said second resist to expose said insulating layer over said second region of said metal layer; etching said insulating layer over said second region of said metal layer and said second region of said metal layer to form at least closely-spaced leads in said second region of said metal layer, said closely-spaced leads being leads spaced apart less than or equal to the thickness of said metal layer; depositing a low-permittivity material between said closely-spaced leads, said low-permittivity material providing a dielectric constant of less than 3 in an region between at least two of said closely-spaced metal leads; and then, depositing a second structural dielectric layer over said widely-spaced leads.
Claim 13
Independent Claim
244 words
A method for patterning a metal layer on a semiconductor wafer, comprising the steps of: depositing a metal layer on a substrate, said metal layer having a first region and a second region; depositing an insulating layer on said metal layer; depositing a first resist on said insulating layer; patterning said first resist to form a conductor pattern on said insulating layer; removing said first resist; covering said insulating layer over said second region of said metal layer with a second resist; etching said insulating layer over said first region of said metal layer and said first region of said metal layer to form widely-spaced leads, said widely-spaced leads having leads spaced apart by more than the thickness of said metal layer; depositing a first structural dielectric layer on said widely-spaced leads; removing said second resist to expose said insulating layer over said second region of said metal layer; etching said insulating layer over said second region of said metal layer and said second region of said metal layer to form at least closely-spaced leads in said second region of said metal layer, said closely-spaced leads being leads spaced apart less than or equal to the thickness of said metal layer; depositing a low-permittivity material between said closely-spaced leads, said low-permittivity material providing a dielectric constant of less than 3 in an region between at least two of said closely-spaced metal leads; and then, depositing a second structural dielectric layer over said widely-spaced leads.
Claim 14
Dependent Claim
19 words
The method of claim 9 wherein all of said closely-spaced leads are formed during said forming closely-spaced leads step.
Claim 15
Dependent Claim
21 words
The method of claim 9 and further comprising the step of depositing a passivation layer, after said forming closely-spaced leads step.
References Cited (Backward Citations)
US4584079A
Cited
US4986878A
Cited
EP0365854A2
Cited
US5004704A
Cited
EP0411795A1
Cited
US5166101A
Cited
US5077234A
Cited
EP0537001A1
Cited
US5272117A
Cited
US5278103A
Cited
US5356513A
Cited
US5324683A
Cited
EP0895592A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-03 | 2002-02-02 | 2002-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-03 | 2006-02-02 | 2006-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-03 | 2010-02-02 | 2010-08-04 | $7700.00 | Window Closed / Lapsed |