Patent US5783471A successfully refreshed from Google Patents.
US5783471A
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US
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Structure and method for improved memory arrays and improved electrical contacts in semiconductor devices
Assignee: Semiconductor Components Industries LLC
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Filing: 1994-11-09
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Granted: 1998-07-21
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Expires: 2014-11-09
Abstract
Abstract A structure and method are provided which reduce memory cell size by forming self-formed contacts and self-aligned source lines in the array. In one embodiment of the present invention, a plurality of self-aligned memory cells are formed in an array. Then, a first insulating layer is deposited on the array, and subsequently etched to form spacers on the sidewalls of each memory cell. Conductive plugs are then formed between adjacent spacers. Subsequently, a second insulating layer is deposited over the array. Finally, drain contacts are formed through the second insulating layer a first set of plugs. Other plugs form source lines for the array. Because the present invention provides a self-formed contact, only the second insulating layer is etched to establish contact between a metal bit line and an underlying diffused drain region. Thus, the present invention ensures appropriate isolation for each memory cell while reducing the area required for contact formation. In this manner, the self-formed contact allows for significant size reduction of the contact pitch. Moreover, using other plugs to form the self-aligned source lines of the array further reduces the size of the word line pitch, thereby dramatically reducing the associated cell size and allowing formation of ultra-high density memory arrays. Additionally, other metal self-aligned source significantly reduces source line resistance, thereby eliminating the need for frequent source line contacts, increasing cell efficiency and improving cell performance.
Inventors
- 👤 Sam Chu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:58
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B41/00; H10B41/40; H10B41/42; H10B41/49; H10D; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/60; H10D64/62; Y; Y10; Y10S; Y10S257/00; Y10S257/905
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
115 words
A method of forming a memory array on a substrate, said method comprising: forming gate structures for a plurality of memory cells on said substrate; forming source/drain regions in said substrate, between said gate structures; depositing a first insulating layer on said gate structures and said substrate; forming from said first insulating layer, sidewall spacers on sidewalls of said gate structures; depositing a first conductive layer which fills spaces between adjacent sidewall spacers; and patterning said first conductive layer to form a first plurality of conductive plugs in contact with a plurality of said source/drain regions, wherein each conductive plug in said first plurality of conductive plugs provides a source line for said memory array.
Claim 2
Independent Claim
115 words
A method of forming a memory array on a substrate, said method comprising: forming gate structures for a plurality of memory cells on said substrate; forming source/drain regions in said substrate, between said gate structures; depositing a first insulating layer on said gate structures and said substrate; forming from said first insulating layer, sidewall spacers on sidewalls of said gate structures; depositing a first conductive layer which fills spaces between adjacent sidewall spacers; and patterning said first conductive layer to form a first plurality of conductive plugs in contact with a plurality of said source/drain regions, wherein each conductive plug in said first plurality of conductive plugs provides a source line for said memory array.
Claim 3
Independent Claim
118 words
A method of forming a memory array on a substrate, said method comprising: forming gate structures for a plurality of memory cells on said substrate; forming source/drain regions in said substrate, between said gate structures; depositing a first insulating layer on said gate structures and said substrate: forming from said first insulating layer, sidewall spacers on sidewalls of said gate structures; depositing a first conductive layer which fills spaces between adjacent sidewall spacers; and patterning said first conductive layer to form a first conductive plug which is in contact with a plurality of said source/drain, wherein patterning said first conductive layer comprises forming a second conductive plug which is in contact with only one of said source/drain regions.
Claim 4
Independent Claim
118 words
A method of forming a memory array on a substrate, said method comprising: forming gate structures for a plurality of memory cells on said substrate; forming source/drain regions in said substrate, between said gate structures; depositing a first insulating layer on said gate structures and said substrate: forming from said first insulating layer, sidewall spacers on sidewalls of said gate structures; depositing a first conductive layer which fills spaces between adjacent sidewall spacers; and patterning said first conductive layer to form a first conductive plug which is in contact with a plurality of said source/drain, wherein patterning said first conductive layer comprises forming a second conductive plug which is in contact with only one of said source/drain regions.
Claim 5
Dependent Claim
37 words
The method of claim 2, further comprising: depositing a second insulating layer on said memory cells and said first and second conductive plugs; and forming a contact through said second insulating layer to said second conductive plug.
Claim 6
Dependent Claim
18 words
The method of claim 1, wherein forming said sidewall spacers includes anisotropic etching of said first insulating layer.
Claim 7
Dependent Claim
13 words
The method of claim 4, wherein said anisotropic etching includes reactive ion etching.
Claim 8
Dependent Claim
23 words
The method of claim 4, wherein patterning said first conductive layer comprises: etching said first conductive layer to form said first conductive plug.
Claim 9
Dependent Claim
26 words
The method of claim 6, wherein etching said first conductive layer is performed such that a portion of said first conductive plug overlaps adjacent gate structures.
Claim 10
Dependent Claim
42 words
The method of claim 3 wherein forming said contact includes: etching said second insulating layer, thereby forming an opening in said second insulating layer and exposing a portion of said second conductive plug; and forming a third conductive plug in said opening.
Claim 11
Dependent Claim
24 words
The method of claim 4, further comprising depositing a glue/barrier layer on said sidewall spacers and said substrate before depositing said first conductive layer.
Claim 12
Dependent Claim
20 words
The method of claim 9, wherein forming of said source/drain regions comprises implanting said substrate before depositing said glue/barrier layer.
Claim 13
Dependent Claim
25 words
The method of claim 1, wherein forming said gate structures comprises forming floating gates and control gates of electrically erasable programmable read only memory cells.
Claim 14
Dependent Claim
50 words
The method of claim 3, wherein forming said contact comprises: forming an opening through said second insulating layer and exposing a portion of said second conductive plug; applying a barrier metal layer to the exposed portion of said second conductive plug; and forming a third conductive plug in said opening.
Claim 15
Dependent Claim
40 words
The method of claim 1, wherein patterning said first conductive layer further comprises forming a second plurality of conductive plugs, wherein each conductive plug in said second plurality is in contact with a corresponding only one of said source/drain regions.
Claim 16
Dependent Claim
57 words
The method of claim 13, further comprising: depositing a second insulating layer on said first and second pluralities of conductive plugs; forming contacts through said second insulating layer to said second plurality of conductive plugs; and forming bit lines overlying said second insulating layer, wherein said bit lines contact said second plurality of plugs via said contacts.
Claim 17
Independent Claim
103 words
A method for forming a memory array, comprising: forming word lines which overlie a semiconductor substrate, wherein a first of the word lines is adjacent a second of the word lines; forming source/drain regions in the substrate between the word lines; forming sidewall spacers on the word lines; and filling a space between the first word line and the second word line with a conductive material, wherein the conductive material between the first and second word lines forms a continuous conductive plug which is in electrical contact with a plurality of the source/drain regions that are between the first and second word lines.
Claim 18
Independent Claim
103 words
A method for forming a memory array, comprising: forming word lines which overlie a semiconductor substrate, wherein a first of the word lines is adjacent a second of the word lines; forming source/drain regions in the substrate between the word lines; forming sidewall spacers on the word lines; and filling a space between the first word line and the second word line with a conductive material, wherein the conductive material between the first and second word lines forms a continuous conductive plug which is in electrical contact with a plurality of the source/drain regions that are between the first and second word lines.
Claim 19
Dependent Claim
25 words
The method of claim 15, wherein the continuous conductive plug between the first and second word lines constitutes a source line of the memory array.
Claim 20
Dependent Claim
61 words
The method of claim 16, further comprising: filling a space between a third word line and a fourth word line with a conductive material; and patterning the conductive material between the third and fourth word lines to form a plurality of isolated conductive plugs, each of the isolated conductive plugs being in electrical contact with only one of the source/drain regions.
Claim 21
Dependent Claim
46 words
The method of claim 17, further comprising: depositing an insulating layer overlying the conductive plugs; forming contacts through the insulating layer to the isolated conductive plugs; and forming bit lines overlying the insulating layer, wherein the bit lines contact the isolated conductive plugs via the contacts.
Claim 22
Dependent Claim
49 words
The method of claim 17, wherein filling the space between the first and second word line and filling the space between the third and fourth word line, comprise depositing a layer of conductive material which overlies the word line and substrate and fills the spaces between the word lines.
Claim 23
Dependent Claim
25 words
The method of claim 19, further comprising forming a glue/barrier layer on the substrate and the sidewall spacers before depositing the layer of conductive material.
Claim 24
Dependent Claim
45 words
The method of claim 15, further comprising patterning the conductive material between the first and second word lines to form a plurality of isolated conductive plugs, each of the isolated conductive plugs being in electrical contact with only a corresponding one of the source/drain regions.
Claim 25
Dependent Claim
51 words
The method of claim 15, wherein forming the sidewall spacers comprises: forming an insulating layer on the word lines and the substrate; and anisotropically etching the insulating layer to expose area of the substrate between the word lines and leave portions of the insulating layer on walls of the word lines.
Claim 26
Dependent Claim
24 words
The method of claim 15, wherein forming the source/drain regions comprises implanting said substrate along straight strips which are perpendicular to said word lines.
Claim 27
Independent Claim
169 words
A method of forming a memory array on a substrate comprising the steps of: forming a plurality of memory cells on said substrate; depositing a first insulating layer on said memory cells and said substrate; forming from said first insulating layer a plurality of sidewall spacers on gate structures of said memory cells; depositing a first conductive layer that fills gaps between said sidewall spacers; partially etching back said first conductive layer to planarize a surface of said first conductive layer; forming a mask on the planarized surface; etching said first conductive layer where exposed by said mask, wherein said etching forms a first conductive plug which fills a first gap between said sidewall spacers and a second conductive plug which fills a second gap between said sidewall spacers, said first plug being electrically isolated from said second plug; depositing a second insulating layer on said memory cells and said first and second conductive plugs; and forming a contact with said first conductive plug through said second insulating layer.
Claim 28
Independent Claim
169 words
A method of forming a memory array on a substrate comprising the steps of: forming a plurality of memory cells on said substrate; depositing a first insulating layer on said memory cells and said substrate; forming from said first insulating layer a plurality of sidewall spacers on gate structures of said memory cells; depositing a first conductive layer that fills gaps between said sidewall spacers; partially etching back said first conductive layer to planarize a surface of said first conductive layer; forming a mask on the planarized surface; etching said first conductive layer where exposed by said mask, wherein said etching forms a first conductive plug which fills a first gap between said sidewall spacers and a second conductive plug which fills a second gap between said sidewall spacers, said first plug being electrically isolated from said second plug; depositing a second insulating layer on said memory cells and said first and second conductive plugs; and forming a contact with said first conductive plug through said second insulating layer.
Claim 29
Dependent Claim
17 words
The method of claim 24, wherein forming said sidewall spacers comprises anisotropically etching said first insulating layer.
Claim 30
Dependent Claim
33 words
The method of claim 24, wherein partially etching back said first conductive layer leaves a portion of said first conductive layer overlying said gate structures and in said gaps between said sidewall spacers.
Claim 31
Dependent Claim
20 words
The method of claim 15, wherein forming source/drain regions comprises implanting said substrate along strips perpendicular to said word lines.
Claim 32
Independent Claim
112 words
A method of forming a memory array on a substrate, said method comprising: forming gate structures for a plurality of memory cells on said substrate; forming source/drain regions in said substrate, between said gate structures; depositing a first insulating layer on said gate structures and said substrate; forming from said first insulating layer, sidewall spacers on sidewalls of said gate structures; depositing a first conductive layer which fills spaces between adjacent sidewall spacers; patterning said first conductive layer to form conductive plugs which contact said source/drain regions; depositing a second insulating layer on said memory cells and said conductive plugs; and forming contacts through said second insulating layer to said conductive plugs.
Claim 33
Independent Claim
112 words
A method of forming a memory array on a substrate, said method comprising: forming gate structures for a plurality of memory cells on said substrate; forming source/drain regions in said substrate, between said gate structures; depositing a first insulating layer on said gate structures and said substrate; forming from said first insulating layer, sidewall spacers on sidewalls of said gate structures; depositing a first conductive layer which fills spaces between adjacent sidewall spacers; patterning said first conductive layer to form conductive plugs which contact said source/drain regions; depositing a second insulating layer on said memory cells and said conductive plugs; and forming contacts through said second insulating layer to said conductive plugs.
Claim 34
Dependent Claim
34 words
The method of claim 28, wherein forming contacts comprises: etching said second insulating layer to expose portions of said conductive plugs; and depositing a second conductive layer on said portions of said conductive plugs.
Claim 35
Dependent Claim
23 words
The method of claim 29, further comprising the step of depositing a third conductive layer over said second insulating layer and said contacts.
Claim 36
Dependent Claim
18 words
The method of claim 29, wherein said portions are smaller than the top surfaces of said conductive plugs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-20 | 2002-01-19 | 2002-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-20 | 2006-01-19 | 2006-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-20 | 2010-01-19 | 2010-07-21 | $7700.00 | Window Closed / Lapsed |