Non-volatile memory and method for fabricating same

Claim 1

A non-volatile memory, comprising: a plurality of cell array regions arranged in parallel with each other, each of said cell array regions crossing a plurality of control gate electrodes and including a plurality of floating gate electrodes each positioned at each crossing point between said control gate electrodes and said cell array regions, a plurality of pairs of source diffusion layers and drain diffusion layers, each of said pairs positioned to bracket a control gate electrode, and source contacts each formed on a corresponding source diffusion layer by self-alignment via said control gate electrodes; a source line connected with each source diffusion layer through a source contact and having drain openings at each area of said drain diffusion layers; a plurality of bit contacts formed within said drain openings; and a plurality of bit lines arranged in parallel with said cell array regions, each bit line being connected with at least one drain diffusion layer through corresponding bit contacts.