Patent US5780929A successfully refreshed from Google Patents.
US5780929A
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Formation of silicided junctions in deep submicron MOSFETS by defect enhanced CoSi2 formation
Assignee: Polaris Innovations Ltd
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Filing: 1996-11-05
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Granted: 1998-07-14
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Expires: 2016-11-05
Abstract
Abstract Deep submicran mosfets with defect enhanced CoSi2 formation and improved silicided junctions. A silicon wafer having a diffusion window is first precleaned with hydrofluoric acid. After the HF precleaning, the silicon wafer is transferred to a conventional cobalt sputtering tool where it is sputter cleaned by bombardment with low energy Ar+ions so as to form an ultra-shallow damage region. After the sputter cleaning, and without removing the wafer from the sputtering tool, Cobalt metal is deposited on the silicon wafer at room temperature and a CoSi2 layer is formed in the diffusion window.
Inventors
- 👤 Heinrich Zeininger
- 👤 Christoph Zeller
- 👤 Udo Schwalke
- 👤 Uwe Doebler
- 👤 Wilfried Haensch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:02
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10P; H10P14/00; H10P14/40; H10P14/42; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/60; H10D64/62; B; B82; B82Y; B82Y30/00; Y; Y10; Y10S; Y10S148/00; Y10S148/017; Y10S148/019; Y10S438/00; Y10S438/974
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
54 words
A MOSFET semiconductor device, comprising: a silicon substrate having a surface with a plurality of monolayers of silicon intentionally damaged by low energy in bombardment; a defect enhanced cobalt silicide layer having no overlying barrier layer associated with said damaged silicon surface; and at least one silicided junction less than 1500 Angstroms in depth.
Claim 2
Dependent Claim
54 words
A MOSFET semiconductor device, comprising: a silicon substrate having a surface with a plurality of monolayers of silicon intentionally damaged by low energy in bombardment; a defect enhanced cobalt silicide layer having no overlying barrier layer associated with said damaged silicon surface; and at least one silicided junction less than 1500 Angstroms in depth.
Claim 3
Dependent Claim
22 words
The device according to claim 1 wherein said cobalt silicide layer comprises CoSi 2 with a thickness of less than 30 nanometers.
Claim 4
Dependent Claim
18 words
The device according to claim 1 further including an oxide isolation region adjacent to said damaged silicon surface.
Claim 5
Dependent Claim
27 words
The device according to claim 1 wherein said surface of said silicon substrate has three to seven monolayers of silicon intentionally damaged by low energy ion bombardment.
Claim 6
Dependent Claim
43 words
The device according to claim 1 wherein said surface of said silicon substrate is damaged by bombardment with low energy Ar+ ions; and wherein said cobalt silicide layer is formed from said damaged silicon substrate surface at room temperature without an annealing step.
Claim 7
Dependent Claim
23 words
The device according to claim 5 wherein said bombardment with low energy Ar+ ions is performed at about 1.5 kev at 1 μA.
Claim 8
Dependent Claim
13 words
The device according to claim 1 wherein said device comprises a sub-micron MOSFET.
Claim 9
Dependent Claim
24 words
The device as recited in claim 1 wherein said plurality of monolayers of silicon intentionally damaged is no greater than twenty monolayers of silicon.
Claim 10
Dependent Claim
24 words
The device as recited in claim 1 wherein said plurality of monolayers of silicon intentionally damaged is from three to seven monolayers of silicon.
Claim 11
Dependent Claim
77 words
A MOSFET semiconductor device, comprising: a defect enhanced cobalt silicide layer having no overlying barrier layer and having a thickness of less than 30 nanometers on a silicon substrate, said silicon substrate initially having a plurality of monolayers of silicon intentionally damaged by low energy ion bombardment, wherein said bombardment causes nucleation sites to be substantially evenly dispersed within said damage region, said monolayers having reacted with cobalt metal deposited thereon to produce said cobalt silicide layer.
Claim 12
Dependent Claim
77 words
A MOSFET semiconductor device, comprising: a defect enhanced cobalt silicide layer having no overlying barrier layer and having a thickness of less than 30 nanometers on a silicon substrate, said silicon substrate initially having a plurality of monolayers of silicon intentionally damaged by low energy ion bombardment, wherein said bombardment causes nucleation sites to be substantially evenly dispersed within said damage region, said monolayers having reacted with cobalt metal deposited thereon to produce said cobalt silicide layer.
Claim 13
Dependent Claim
15 words
The device according to claim 10 wherein said cobalt silicide layer comprises CoSi 2 .
Claim 14
Dependent Claim
41 words
The device according to claim 10 having junctions of less than 1500 Angstroms and no agglomeration of silicides, and wherein said cobalt silicide layer on said silicon substrate forms a contact with sheet resistance of less than five ohms per Square.
Claim 15
Dependent Claim
25 words
The device according to claim 10 wherein said low energy ion bombardment comprises bombardment with low energy Ar+ ions at 1.5 kev at 1 μA.
Claim 16
Dependent Claim
21 words
The device according to claim 10 wherein said cobalt silicide layer is formed at room temperature with no further annealing step.
Claim 17
Dependent Claim
13 words
The device according to claim 10 wherein said device comprises a sub-micron MOSFET.
Claim 18
Dependent Claim
24 words
The device as recited in claim 10 wherein said plurality of monolayers of silicon intentionally damaged is no greater than twenty monolayers of silicon.
Claim 19
Dependent Claim
24 words
The device as recited in claim 10 wherein said plurality of monolayers of silicon intentionally damaged is from three to seven monolayers of silicon.
Claim 20
Dependent Claim
19 words
The device recited in claim 10 further comprising at least one silicided junction less than 1500 Angstroms in depth.
Claim 21
Dependent Claim
80 words
An improved submicron MOSFET semiconductor device comprising: a semiconductor body having a surface with a plurality of monolayers of silicon intentionally damaged by low energy ion bombardment, wherein said plurality of monlayers of silicon intentionally damaged is at least three monolayers of silicon and no greater than twenty monlayers of silicon; and a defect enhanced cobalt silicide layer less than 30 nanometers in depth associated with said damaged silicon surface, wherein said cobalt silicide layer has no overlying barrier layer.
Claim 22
Dependent Claim
80 words
An improved submicron MOSFET semiconductor device comprising: a semiconductor body having a surface with a plurality of monolayers of silicon intentionally damaged by low energy ion bombardment, wherein said plurality of monlayers of silicon intentionally damaged is at least three monolayers of silicon and no greater than twenty monlayers of silicon; and a defect enhanced cobalt silicide layer less than 30 nanometers in depth associated with said damaged silicon surface, wherein said cobalt silicide layer has no overlying barrier layer.
Claim 23
Dependent Claim
20 words
The device as recited in claim 19 further comprising at least one silicided junction less than 1500 Angstroms in depth.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-13 | 2002-01-12 | 2002-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-13 | 2006-01-12 | 2006-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-13 | 2010-01-12 | 2010-07-14 | $7700.00 | Window Closed / Lapsed |