US5780351A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having capacitor and manufacturing method thereof
Assignee: Panasonic Holdings Corp
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Filing: 1997-04-28
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Granted: 1998-07-14
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Expires: 2017-04-28
Abstract
Abstract A semi conductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm 3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10 21 atoms/cm 3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
Inventors
- 👤 Koji Arita
- 👤 Eiji Fujii
- 👤 Yasuhiro Shimada
- 👤 Yasuhiro Uemoto
- 👤 Toru Nasu
- 👤 Akihiro Matsuda
- 👤 Yoshihisa Nagano
- 👤 Atsuo Inoue
- 👤 Taketoshi Matsuura
- 👤 Tatsuo Otsuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:44
CPC Classifications
H; H10; H10B; H10B53/00; H10D; H10D84/00; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B51/00; H10B51/30; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10D1/692; H10D1/696; Y; Y10; Y10S; Y10S438/00; Y10S438/958
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
156 words
A method of manufacturing a semiconductor device comprising the steps of: forming a capacitor comprising, a bottom electrode having a conductive layer, a capacitor dielectric layer having one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode having a conductive layer formed on the capacitor dielectric layer, on an insulating layer of a semiconductor substrate in which an integrated circuit is fabricated; forming an interlayer insulating layer by covering the capacitor; forming contact holes reaching the integrated circuit, top electrode and bottom electrode of the capacitor, through the insulating layer and interlayer insulating layer; forming interconnections to be electrically connected with the integrated circuit and capacitor through the contact holes; forming a second interlayer insulating layer by covering the interconnections; removing the second interlayer insulating layer above the capacitor, after the step of forming interconnections; heating the capacitor; and forming a passivation layer by covering the interconnections.
Claim 2
Independent Claim
156 words
A method of manufacturing a semiconductor device comprising the steps of: forming a capacitor comprising, a bottom electrode having a conductive layer, a capacitor dielectric layer having one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode having a conductive layer formed on the capacitor dielectric layer, on an insulating layer of a semiconductor substrate in which an integrated circuit is fabricated; forming an interlayer insulating layer by covering the capacitor; forming contact holes reaching the integrated circuit, top electrode and bottom electrode of the capacitor, through the insulating layer and interlayer insulating layer; forming interconnections to be electrically connected with the integrated circuit and capacitor through the contact holes; forming a second interlayer insulating layer by covering the interconnections; removing the second interlayer insulating layer above the capacitor, after the step of forming interconnections; heating the capacitor; and forming a passivation layer by covering the interconnections.
Claim 3
Dependent Claim
27 words
The manufacturing method of claim 1, wherein the step of heating the capacitor comprises, heating in inert gas or in vacuum, and heating in gas containing oxygen.
Claim 4
Dependent Claim
22 words
The manufacturing method of claim 1, wherein the step of heating the capacitor is carried out before the step of forming interconnections.
Claim 5
Dependent Claim
22 words
The manufacturing method of claim 1, wherein the step of heating the capacitor is carried out after the step of forming interconnections.
Claim 6
Dependent Claim
30 words
The manufacturing method of semiconductor device of claim 1, wherein the step of heating the capacitor comprises, heating in inert gas or in vacuum, and heating in gas containing oxygen.
Claim 7
Dependent Claim
190 words
A manufacturing method of semiconductor device comprising: a step of forming a capacitor comprising a bottom electrode composed of a conductive layer, a capacitor dielectric layer composed of one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor dielectric layer, on an insulating layer of a semiconductor substrate in which an integrated circuit is fabricated, a step of forming an interlayer insulating layer by covering the capacitor, a step of forming contact holes reaching the integrated circuit, and top electrode and bottom electrode of the capacitor, through the insulating layer and interlayer insulating layer, a step of forming interconnections to be electrically connected with the integrated circuit and capacitor through the contact holes, a step of forming a passivation layer by covering the interconnections, a step of removing only the passivation layer above the top electrode of the capacitor or both the interlayer insulating layer and passivation layer, a step of heating the capacitor, and a step of forming a second passivation layer by covering the upper part of the top electrode.
Claim 8
Dependent Claim
190 words
A manufacturing method of semiconductor device comprising: a step of forming a capacitor comprising a bottom electrode composed of a conductive layer, a capacitor dielectric layer composed of one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor dielectric layer, on an insulating layer of a semiconductor substrate in which an integrated circuit is fabricated, a step of forming an interlayer insulating layer by covering the capacitor, a step of forming contact holes reaching the integrated circuit, and top electrode and bottom electrode of the capacitor, through the insulating layer and interlayer insulating layer, a step of forming interconnections to be electrically connected with the integrated circuit and capacitor through the contact holes, a step of forming a passivation layer by covering the interconnections, a step of removing only the passivation layer above the top electrode of the capacitor or both the interlayer insulating layer and passivation layer, a step of heating the capacitor, and a step of forming a second passivation layer by covering the upper part of the top electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-13 | 2002-01-12 | 2002-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-13 | 2006-01-12 | 2006-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-13 | 2010-01-12 | 2010-07-14 | $7700.00 | Window Closed / Lapsed |